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| | == Architecture == | | == Architecture == |
| − | [[File:intel lakefield overview.png|right|thumb|Lakefield Architectre]]
| + | * [[3d integrated circuit]] |
| − | * [[3D integrated circuit]] | |
| | ** {{intel|Foveros}} packaging | | ** {{intel|Foveros}} packaging |
| | ** [[22 nm]] base field | | ** [[22 nm]] base field |
| | ** [[10 nm]] compute field | | ** [[10 nm]] compute field |
| − | *** single-ISA heterogeneous multi-core
| + | *** 1x {{\\|Sunny Cove}} [[big core]] |
| − | **** 1x {{\\|Sunny Cove}} [[big core]]
| + | *** 4x {{\\|Tremont}} [[small cores]] |
| − | **** 4x {{\\|Tremont}} [[small cores]]
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| | * GPU | | * GPU |
| | ** {{\\|Gen11}} graphics | | ** {{\\|Gen11}} graphics |
| − | ** {{\\|Gen11}}.5 display engine
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| − | * IPU
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| − | ** IPU 5.5
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| | * Memory | | * Memory |
| | ** LPDDR4X up to 4266 MT/s | | ** LPDDR4X up to 4266 MT/s |
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| | == Overview == | | == Overview == |
| − | Lakefield is [[Intel's]] first production [[three-dimensional integrated circuit]] single-[[ISA]] [[penta-core]] [[heterogeneous multi-core architecture]]. The SoC features a compute die that rests directly on a base die using Intel's {{intel|Foveros}} face-to-face 3D integration technology. The [[package on package|PoP]] memory then sits on top of the compute die connected via [[wirebond]]. The entire SoC is a single package measuring 12 mm by 12 mm by 1 mm.
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| − | Lakefield started as an initiative from Intel to create a new class of compute devices with high performance in a mobile phone form factor. To that end, Lakefield barrows requirements from both desktop/laptop and smartphone including high-performance cores, always-on capabilities, always-on connectivity, and ultra-low 2-3 milliwatts range standby power. Lakefield main compute die is fabricated on Intel's [[intel 10nm|10 nm process]] for it's high-power and efficiency capabilities while the base die is fabricated on the company's [[22FFL|22 nm (22FFL) process]] for its ultra-low power capabilities. Lakefield provides a gen-over-gen improvement of 1/10th the standby power, 50% graphics performance improvement, 40% total core area reduction, and 40% Z-height reduction.
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| − | == Compute die ==
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| − | The compute die is fabricated on Intel's [[intel 10nm|10 nm process]] for high performance and high power efficiency. This die features all the compute-related IPs. It incorporates a single {{\\|Sunny Cove}} [[big core]] along with a quad-core cluster of {{\\|Tremont}} [[small cores]]. This die also integrates IPU 5.5, {{\\|Gen11}} graphics and media along with a Gen11.5 display engine, and quad-channel (16-bit) LPDDR4x memory. The IPU 5.5 supports up to 6 connected camera at 16 MP while the Gen 11.5 display supports 4 pipes and two displays with a 5K @ 60 Hz or 4K @ 120 Hz resolution.
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| − | === Heterogeneous cores ===
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| − | {{see also|intel/microarchitectures/sunny cove|intel/microarchitectures/tremont|l1=Sunny Cove|l2=Tremont}}
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| − | [[File:lkf big vs small st.jpg|thumb|right|{{\\|Sunny Cove}} vs {{\\|Tremont}} core in ST perf]]
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| − | [[File:lkf big vs small mt.jpg|thumb|right|{{\\|Sunny Cove}} vs 4x{{\\|Tremont}} cores in MT perf]]
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| − | Lakefield compute die features a hybrid architecture with single big core along with four small cores. The architecture utilizes a single-ISA, thus having {{x86|AVX}} and {{x86|AVX-512}} disabled on the big cores in order to enable a seamless migration of workloads between cores. The big {{\\|Sunny Cove}} core is designed for high-performance and bursty workloads while light-weight and threaded applications can utilize the {{\\|Tremont}} cores for higher power-efficiency. The combination of both types of cores allow for a wider power/performance curve beyond what is possible with just a single type of core.
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| − | On Intel's 10-nanometer process, four {{\\|Tremont}} cores along with their 1.5 MiB of [[L2 cache]] fit within the silicon area of a single {{\\|Sunny Cove}} core. The single {{\\|Sunny cove}} core yields the best power-performance efficiency at the higher end of the perf/power curve but loses to the {{\\|Tremont}} core at the low-end. Likewise, the four {{\\|Tremont}} cores can extend the multi-thread capabilities by over 100% over the {{\\|Sunny Cove}} core while doing so at much higher power efficiency.
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| − | Lakefield dynamically provides feedback to the OS/SW regarding the power and performance characteristics of the workload. Workloads that exhibit performance or high responsiveness are given an indication to get scheduled on the {{\\|Sunny Cove}} cores. Likewise, background threads are given an indication to get scheduled on the {{\\|Tremont}} cores. The feedback can be used for the OS to dynamically migrate threads to provide the best power and power efficiency.
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| − | == Base die ==
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| − | The BASE die is designed for ultra-low power always-on capabilities. This die integrates power delivery, security, storage, audio, USB 2 and 3, UFS3, PCIe Gen3, ISH, I3C, SDIO, CSE, TC SS, SPI/I2C.
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| − | == Power delivery ==
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| − | Lakefield uses a [[power management integrated circuit]] (PMIC) instead of a discrete [[voltage regulator module|VR]] or [[fully-integrated voltage regulator|FIVR]] as with its contemporaries such as {{\\|Ice Lake (client)|Ice Lake}}. To support Lakefield, two PMICs are required - one PMIC for the compute die and one for the base die (CSC and WRC).
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| − | == Bibliography ==
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| − | * {{bib|hc|31|Intel}}
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