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Latest revision | Your text | ||
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| {{intel|Kaby Lake S|l=core}} || KBL-S || || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis | | {{intel|Kaby Lake S|l=core}} || KBL-S || || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis | ||
|- | |- | ||
− | | {{intel|Kaby Lake G|l=core}} || KBL-G || | + | | {{intel|Kaby Lake G|l=core}} || KBL-G || || Gaming Chip || GT2 + AMD {{amd|Vega|l=arch}} || Kaby Lake + Radeon Vega 20/24 |
|- | |- | ||
| {{intel|Kaby Lake X|l=core}} || KBL-X || {{intel|Basin Falls|l=platform}} || Extreme Performance || || High-end desktops & enthusiasts market | | {{intel|Kaby Lake X|l=core}} || KBL-X || {{intel|Basin Falls|l=platform}} || Extreme Performance || || High-end desktops & enthusiasts market | ||
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=== CPUID === | === CPUID === | ||
− | {| class="wikitable tc1 tc2 tc3 tc4 | + | {| class="wikitable tc1 tc2 tc3 tc4" |
− | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | + | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model |
|- | |- | ||
− | | rowspan="2" | {{intel|Kaby Lake Y|Y|l=core}}/{{intel|Kaby Lake U|U|l=core}}/{{intel|Kaby Lake R|R|l=core}} || 0 || 0x6 || 0x8 || 0xE | + | | rowspan="2" | {{intel|Kaby Lake Y|Y|l=core}}/{{intel|Kaby Lake U|U|l=core}}/{{intel|Kaby Lake R|R|l=core}} || 0 || 0x6 || 0x8 || 0xE |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model 142 |
|- | |- | ||
− | | rowspan="2" | {{intel|Kaby Lake DT|DT|l=core}}/{{intel|Kaby Lake H|H|l=core}}/{{intel|Kaby Lake S|S|l=core}}/{{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE | + | | rowspan="2" | {{intel|Kaby Lake DT|DT|l=core}}/{{intel|Kaby Lake H|H|l=core}}/{{intel|Kaby Lake S|S|l=core}}/{{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model 158 |
|} | |} | ||
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* Families | * Families | ||
− | ** {{intel|Core i3}} processors dropped support for ECC memory | + | ** {{intel|Core i3}} processors dropped support for ECC memory (except for Embedded models) |
** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ||
** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support | ** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support | ||
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**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
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== Core == | == Core == | ||
− | |||
− | |||
− | |||
=== Pipeline === | === Pipeline === | ||
{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | {{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | ||
Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | ||
+ | |||
+ | ==== Scheduler Ports & Execution Units ==== | ||
+ | <table class="wikitable"> | ||
+ | <tr><th colspan="2">Scheduler Ports Designation</th></tr> | ||
+ | <tr><th rowspan="5">Port 0</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops</td></tr> | ||
+ | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr> | ||
+ | <tr><td>Integer/FP Division and [[Square Root]]</td></tr> | ||
+ | <tr><td>[[AES]] Encryption</td></tr> | ||
+ | <tr><td>Branch2</td></tr> | ||
+ | <tr><th rowspan="2">Port 1</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning</td></tr> | ||
+ | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr> | ||
+ | <tr><th rowspan="3">Port 5</th><td>Integer/Vector Arithmetic, Logic</td></tr> | ||
+ | <tr><td>Vector Permute</td></tr> | ||
+ | <tr><td>[[x87]] FP Add, Composite Int, CLMUL</td></tr> | ||
+ | <tr><th rowspan="2">Port 6</th><td>Integer Arithmetic, Logic, Shift</td></tr> | ||
+ | <tr><td>Branch</td></tr> | ||
+ | <tr><th>Port 2</th><td>Load, AGU</td></tr> | ||
+ | <tr><th>Port 3</th><td>Load, AGU</td></tr> | ||
+ | <tr><th>Port 4</th><td>Store, AGU</td></tr> | ||
+ | <tr><th>Port 7</th><td>AGU</td></tr> | ||
+ | </table> | ||
+ | |||
+ | {| class="wikitable collapsible collapsed" | ||
+ | |- | ||
+ | ! colspan="3" | Execution Units | ||
+ | |- | ||
+ | ! Execution Unit !! # of Units !! Instructions | ||
+ | |- | ||
+ | | ALU || 4 || add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup* | ||
+ | |- | ||
+ | | DIV || 1 || divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv | ||
+ | |- | ||
+ | | Shift || 2 || sal, shl, rol, adc, sarx, adcx, adox, etc... | ||
+ | |- | ||
+ | | Shuffle || 1 || (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw | ||
+ | |- | ||
+ | | Slow Int || 1 || mul, imul, bsr, rcl, shld, mulx, pdep, etc... | ||
+ | |- | ||
+ | | Bit Manipulation || 2 || andn, bextr, blsi, blsmsk, bzhi, etc | ||
+ | |- | ||
+ | | FP Mov || 1 || (v)movsd/ss, (v)movd gpr | ||
+ | |- | ||
+ | | SIMD Misc || 1 || STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm | ||
+ | |- | ||
+ | | Vec ALU || 3 || (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd | ||
+ | |- | ||
+ | | Vec Shift || 2 || (v)psllv*, (v)psrlv*, vector shift count in imm8 | ||
+ | |- | ||
+ | | Vec Add || 2 || (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si | ||
+ | |- | ||
+ | | Vec Mul || 2 || (v)mul*, (v)pmul*, (v)pmadd* | ||
+ | |- | ||
+ | |colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included. | ||
+ | |} | ||
== Configurability == | == Configurability == | ||
− | Kaby Lake builds upon the Skylake architecture, most dies are slight | + | Kaby Lake builds upon the Skylake architecture, most dies are slight enchantments of their Skylake counterparts. The biggest change is the removal of the high performance quad core GT4 die, which has been replaced by the Kaby Lake G processors. And the introduction of the first low power quad core processor. |
<gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:right"> | <gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:right"> |
Facts about "Kaby Lake - Microarchitectures - Intel"
codename | Kaby Lake + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/kaby lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Kaby Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |