From WikiChip
Editing intel/microarchitectures/kaby lake
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 14: | Line 14: | ||
|stages min=14 | |stages min=14 | ||
|stages max=19 | |stages max=19 | ||
− | |isa=x86-64 | + | |isa=x86-16 |
+ | |isa 2=x86-32 | ||
+ | |isa 3=x86-64 | ||
|extension=MOVBE | |extension=MOVBE | ||
|extension 2=MMX | |extension 2=MMX | ||
Line 62: | Line 64: | ||
|core name=Kaby Lake Y | |core name=Kaby Lake Y | ||
|core name 2=Kaby Lake U | |core name 2=Kaby Lake U | ||
− | |core name 3=Kaby Lake | + | |core name 3=Kaby Lake H |
− | |core name 4=Kaby Lake | + | |core name 4=Kaby Lake R |
− | |core name 5=Kaby Lake | + | |core name 5=Kaby Lake S |
− | |core name 6=Kaby Lake | + | |core name 6=Kaby Lake DT |
− | |core name 7 | + | |core name 7=Kaby Lake X |
− | |||
|predecessor=Skylake | |predecessor=Skylake | ||
|predecessor link=intel/microarchitectures/skylake | |predecessor link=intel/microarchitectures/skylake | ||
|successor=Coffee Lake | |successor=Coffee Lake | ||
|successor link=intel/microarchitectures/coffee lake | |successor link=intel/microarchitectures/coffee lake | ||
− | |successor 2= | + | |successor 2=Cannonlake |
− | |successor 2 link=intel/microarchitectures/ | + | |successor 2 link=intel/microarchitectures/cannonlake |
+ | |pipeline=Yes | ||
+ | |OoOE=Yes | ||
+ | |issues=5 | ||
+ | |core names=Yes | ||
}} | }} | ||
[[File:7th Gen Core-i7-badge.png|thumb|right|175px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]] | [[File:7th Gen Core-i7-badge.png|thumb|right|175px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]] | ||
− | '''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\| | + | '''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops, servers, and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\|Cannonlake}} was originally set to replace {{\\|Skylake}} as the next microarchitecture using a [[10 nm process]], however Intel later revised their roadmap to include Kaby Lake (with Cannonlake being pushed back to [[2017]]). |
For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For workstation class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}. There are no Kaby Lake-based server microprocessors. | For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For workstation class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}. There are no Kaby Lake-based server microprocessors. | ||
Line 83: | Line 88: | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Core !! Abbrev !! | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
|- | |- | ||
− | | {{intel|Kaby Lake Y|l=core}} || KBL-Y | + | | {{intel|Kaby Lake Y|l=core}} || KBL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks |
|- | |- | ||
− | | {{intel|Kaby Lake U|l=core}} || KBL-U | + | | {{intel|Kaby Lake U|l=core}} || KBL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
|- | |- | ||
− | | {{intel|Kaby Lake R|l=core}} || KBL-R | + | | {{intel|Kaby Lake R|l=core}} || KBL-R || Ultra-low Power || GT2 || Kaby Lake U Refresh |
|- | |- | ||
− | | {{intel|Kaby Lake H|l=core}} || KBL-H | + | | {{intel|Kaby Lake H|l=core}} || KBL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations |
|- | |- | ||
− | | {{intel|Kaby Lake S|l=core}} || KBL-S | + | | {{intel|Kaby Lake S|l=core}} || KBL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis |
|- | |- | ||
− | | {{intel|Kaby Lake G|l=core}} || KBL-G || | + | | {{intel|Kaby Lake G|l=core}} || KBL-G || || || Kaby Lake + ? |
|- | |- | ||
− | | {{intel|Kaby Lake X|l=core}} || KBL-X | + | | {{intel|Kaby Lake X|l=core}} || KBL-X || Extreme Performance || || High-end desktops & enthusiasts market |
|- | |- | ||
− | | {{intel|Kaby Lake DT|l=core}} || KBL-DT | + | | {{intel|Kaby Lake DT|l=core}} || KBL-DT || Workstation || GT2 || Workstations & entry-level servers |
|} | |} | ||
Line 114: | Line 119: | ||
|- | |- | ||
| rowspan="2" | [[File:intel pentium (2015).png|50px|link=intel/pentium_(2009)]] || rowspan="2" | {{intel|Pentium (2009)|Pentium}} || style="text-align: left;" | Budget (Mobile) || rowspan="2" | dual || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} | | rowspan="2" | [[File:intel pentium (2015).png|50px|link=intel/pentium_(2009)]] || rowspan="2" | {{intel|Pentium (2009)|Pentium}} || style="text-align: left;" | Budget (Mobile) || rowspan="2" | dual || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} | ||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
| style="text-align: left;" | Budget (Desktop) || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} | | style="text-align: left;" | Budget (Desktop) || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} | ||
Line 139: | Line 140: | ||
== Release Dates == | == Release Dates == | ||
− | Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017. The | + | Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017. The enthusiasts version, {{intel|Kaby Lake X|l=core}}, was introduced during Computex Taipei 2017. |
− | On August 21 2017, Intel introduced 8th generation mobile processors ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}}) which is also based on the | + | On August 21 2017, Intel introduced 8th generation mobile processors ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}}) which is also based on the Kaby Lake microarchitecture and doubles the core (4 from 2) of many mainstream mobile microprocessors. |
== Process Technology == | == Process Technology == | ||
Line 166: | Line 167: | ||
== Compatibility == | == Compatibility == | ||
− | There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. | + | There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. Microsoft announced that only [[Windows 10]] will have support for Kaby Lake. [[Linux]] added initial support for Kaby Lake starting with Linux Kernel 4.5. |
{| class="wikitable" | {| class="wikitable" | ||
! Vendor !! OS !! Version !! Notes | ! Vendor !! OS !! Version !! Notes | ||
|- | |- | ||
− | | rowspan="3" | | + | | rowspan="3" | Microsoft || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support |
|- | |- | ||
| style="background-color: #ffdad6;" | Windows 8 || No Support | | style="background-color: #ffdad6;" | Windows 8 || No Support | ||
Line 199: | Line 200: | ||
=== CPUID === | === CPUID === | ||
− | {| class="wikitable tc1 tc2 tc3 tc4 | + | {| class="wikitable tc1 tc2 tc3 tc4" |
− | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | + | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model |
|- | |- | ||
− | | rowspan="2" | {{intel|Kaby Lake Y|Y|l=core}}/{{intel|Kaby Lake U|U | + | | rowspan="2" | {{intel|Kaby Lake Y|Y|l=core}}/{{intel|Kaby Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model 142 |
|- | |- | ||
− | | rowspan="2" | {{intel|Kaby Lake DT|DT|l=core}}/{{intel|Kaby Lake H|H|l=core}}/{{intel|Kaby Lake S|S|l=core}}/{{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE | + | | rowspan="2" | {{intel|Kaby Lake DT|DT|l=core}}/{{intel|Kaby Lake H|H|l=core}}/{{intel|Kaby Lake S|S|l=core}}/{{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model 158 |
|} | |} | ||
Line 228: | Line 229: | ||
* Memory | * Memory | ||
** Faster memory for mainstream desktops (i.e., {{intel|Kaby Lake S|l=core}}) DDR4-2400 (from DDR4-2133) | ** Faster memory for mainstream desktops (i.e., {{intel|Kaby Lake S|l=core}}) DDR4-2400 (from DDR4-2133) | ||
− | ** Faster memory for high- | + | ** Faster memory for high-ferf mobile (i.e., {{intel|Kaby Lake H|l=core}}) DDR4-2400 (from DDR4-2133) |
* Interfaces | * Interfaces | ||
Line 245: | Line 246: | ||
* Families | * Families | ||
− | ** {{intel|Core i3}} processors dropped support for ECC memory | + | ** {{intel|Core i3}} processors dropped support for ECC memory (except for Embedded models) |
** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ||
** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support | ** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support | ||
Line 332: | Line 333: | ||
**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
Line 342: | Line 343: | ||
**** fixed partition | **** fixed partition | ||
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= --> | <!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= --> | ||
− | |||
− | |||
− | |||
== Core == | == Core == | ||
− | |||
− | |||
− | |||
=== Pipeline === | === Pipeline === | ||
{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | {{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | ||
Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | ||
− | == | + | ==== Scheduler Ports & Execution Units ==== |
+ | <table class="wikitable"> | ||
+ | <tr><th colspan="2">Scheduler Ports Designation</th></tr> | ||
+ | <tr><th rowspan="5">Port 0</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops</td></tr> | ||
+ | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr> | ||
+ | <tr><td>Integer/FP Division and [[Square Root]]</td></tr> | ||
+ | <tr><td>[[AES]] Encryption</td></tr> | ||
+ | <tr><td>Branch2</td></tr> | ||
+ | <tr><th rowspan="2">Port 1</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning</td></tr> | ||
+ | <tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr> | ||
+ | <tr><th rowspan="3">Port 5</th><td>Integer/Vector Arithmetic, Logic</td></tr> | ||
+ | <tr><td>Vector Permute</td></tr> | ||
+ | <tr><td>[[x87]] FP Add, Composite Int, CLMUL</td></tr> | ||
+ | <tr><th rowspan="2">Port 6</th><td>Integer Arithmetic, Logic, Shift</td></tr> | ||
+ | <tr><td>Branch</td></tr> | ||
+ | <tr><th>Port 2</th><td>Load, AGU</td></tr> | ||
+ | <tr><th>Port 3</th><td>Load, AGU</td></tr> | ||
+ | <tr><th>Port 4</th><td>Store, AGU</td></tr> | ||
+ | <tr><th>Port 7</th><td>AGU</td></tr> | ||
+ | </table> | ||
− | + | {| class="wikitable collapsible collapsed" | |
− | + | |- | |
− | + | ! colspan="3" | Execution Units | |
− | + | |- | |
− | + | ! Execution Unit !! # of Units !! Instructions | |
− | + | |- | |
− | + | | ALU || 4 || add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup* | |
− | + | |- | |
− | + | | DIV || 1 || divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv | |
− | + | |- | |
− | {{ | + | | Shift || 2 || sal, shl, rol, adc, sarx, adcx, adox, etc... |
+ | |- | ||
+ | | Shuffle || 1 || (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw | ||
+ | |- | ||
+ | | Slow Int || 1 || mul, imul, bsr, rcl, shld, mulx, pdep, etc... | ||
+ | |- | ||
+ | | Bit Manipulation || 2 || andn, bextr, blsi, blsmsk, bzhi, etc | ||
+ | |- | ||
+ | | FP Mov || 1 || (v)movsd/ss, (v)movd gpr | ||
+ | |- | ||
+ | | SIMD Misc || 1 || STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm | ||
+ | |- | ||
+ | | Vec ALU || 3 || (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd | ||
+ | |- | ||
+ | | Vec Shift || 2 || (v)psllv*, (v)psrlv*, vector shift count in imm8 | ||
+ | |- | ||
+ | | Vec Add || 2 || (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si | ||
+ | |- | ||
+ | | Vec Mul || 2 || (v)mul*, (v)pmul*, (v)pmadd* | ||
+ | |- | ||
+ | |colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included. | ||
+ | |} | ||
== Graphics == | == Graphics == | ||
{{main|intel/microarchitectures/gen9.5|l1=Gen9.5}} | {{main|intel/microarchitectures/gen9.5|l1=Gen9.5}} | ||
− | Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, | + | Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, an [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Kaby Lake's biggest enhancement is the addition of native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit). |
{| class="wikitable tc2 tc3" | {| class="wikitable tc2 tc3" | ||
Line 384: | Line 419: | ||
| {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || - | | {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || - | ||
|- | |- | ||
− | | {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U | + | | {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || - |
|- | |- | ||
| {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || - | | {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || - | ||
Line 451: | Line 486: | ||
=== Overclocking === | === Overclocking === | ||
See {{intel|Skylake#Overclocking|Skylake §Overclocking|l=arch}}. | See {{intel|Skylake#Overclocking|Skylake §Overclocking|l=arch}}. | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Die == | == Die == | ||
Line 563: | Line 547: | ||
* [[14 nm process|14 nm+ process]] | * [[14 nm process|14 nm+ process]] | ||
* 11 metal layers | * 11 metal layers | ||
− | |||
* ~126 mm² die size | * ~126 mm² die size | ||
* 4 CPU cores + 24 GPU EUs | * 4 CPU cores + 24 GPU EUs | ||
− | : [[File:kaby lake (quad core).png | + | : [[File:kaby lake (quad core).png|650px]] |
Line 573: | Line 556: | ||
=== Quad-Core (Mobile {{intel|Kaby Lake R|l=core}}) === | === Quad-Core (Mobile {{intel|Kaby Lake R|l=core}}) === | ||
− | With the introduction of {{intel|Kaby Lake R|l=core}}, a new quad-core die was introduced | + | With the introduction of {{intel|Kaby Lake R|l=core}}, a new quad-core die was introduced with the IPU in the System Agent. |
* [[14 nm process|14 nm+ process]] | * [[14 nm process|14 nm+ process]] | ||
Line 607: | Line 590: | ||
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">Cores</th><th data-sort-type="number">Threads</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr> | <tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">Cores</th><th data-sort-type="number">Threads</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr> | ||
<tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Uniprocessors]]</th></tr> | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Uniprocessors]]</th></tr> | ||
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::!Kaby Lake R | + | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::!Kaby Lake R]] |
|?full page name | |?full page name | ||
|?model number | |?model number | ||
Line 646: | Line 629: | ||
<tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">8th Generation ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}})</th></tr> | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">8th Generation ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}})</th></tr> | ||
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::Kaby Lake R]] | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::Kaby Lake R]] | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
Line 736: | Line 681: | ||
=== 8th Generation === | === 8th Generation === | ||
* [[:File:kaby-lake-r-product-brief.pdf|Kaby Lake R Product Brief]] | * [[:File:kaby-lake-r-product-brief.pdf|Kaby Lake R Product Brief]] | ||
− | |||
− | |||
− | == | + | == References == |
* Intel Developer Forum 2015, San Francisco, August 18-20, 2015 | * Intel Developer Forum 2015, San Francisco, August 18-20, 2015 | ||
* Intel Technology and Manufacturing Day, March 28, 2017 | * Intel Technology and Manufacturing Day, March 28, 2017 | ||
− | |||
− | |||
− | |||
== Artwork == | == Artwork == | ||
Line 761: | Line 701: | ||
File:7th-gen-wafer.jpg|7th gen core silicon wafers | File:7th-gen-wafer.jpg|7th gen core silicon wafers | ||
</gallery> | </gallery> | ||
+ | |||
+ | == External Links == | ||
+ | * [https://www.youtube.com/watch?v=3zoD3_ZZeaw Kaby Lake – All CPUs Benchmarks ROUNDUP] | ||
== See also == | == See also == | ||
* {{amd|microarchitectures/zen|AMD's Zen}} | * {{amd|microarchitectures/zen|AMD's Zen}} |
Facts about "Kaby Lake - Microarchitectures - Intel"
codename | Kaby Lake + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/kaby lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Kaby Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |