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{{intel title|Kaby Lake|arch}} | {{intel title|Kaby Lake|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | + | | name = Kaby Lake | |
− | |name=Kaby Lake | + | | designer = Intel |
− | |designer=Intel | + | | manufacturer = Intel |
− | |manufacturer=Intel | + | | introduction = August 30, 2016 |
− | |introduction=August 30, 2016 | + | | phase-out = |
− | |process=14 nm | + | | process = 14 nm |
− | |cores=2 | + | | cores = 2 |
− | |cores 2=4 | + | | cores 2 = 4 |
− | |type=Superscalar | + | | cores 3 = 6 |
− | |speculative=Yes | + | | cores 4 = 8 |
− | |renaming=Yes | + | | cores 5 = 10 |
− | |stages min=14 | + | | cores 6 = 12 |
− | |stages max=19 | + | | cores 7 = 14 |
− | | | + | | cores 8 = 16 |
− | |extension=MOVBE | + | | cores 9 = 18 |
− | |extension 2=MMX | + | | cores 10 = 20 |
− | |extension 3=SSE | + | | cores 11 = 22 |
− | |extension 4=SSE2 | + | |
− | |extension 5=SSE3 | + | | pipeline = Yes |
− | |extension 6=SSSE3 | + | | type = Superscalar |
− | |extension 7=SSE4.1 | + | | OoOE = Yes |
− | |extension 8=SSE4.2 | + | | speculative = Yes |
− | |extension 9=POPCNT | + | | renaming = Yes |
− | |extension 10=AVX | + | | isa = IA-32 |
− | |extension 11=AVX2 | + | | isa 2 = x86-64 |
− | |extension 12=AES | + | | stages min = 14 |
− | |extension 13=PCLMUL | + | | stages max = 19 |
− | |extension 14=FSGSBASE | + | | issues = 4 |
− | |extension 15=RDRND | + | |
− | |extension 16=FMA3 | + | | inst = Yes |
− | |extension 17=F16C | + | | feature = |
− | |extension 18=BMI | + | | extension = MOVBE |
− | |extension 19=BMI2 | + | | extension 2 = MMX |
− | |extension 20=VT-x | + | | extension 3 = SSE |
− | |extension 21=VT-d | + | | extension 4 = SSE2 |
− | |extension 22=TXT | + | | extension 5 = SSE3 |
− | |extension 23=TSX | + | | extension 6 = SSSE3 |
− | |extension 24=RDSEED | + | | extension 7 = SSE4.1 |
− | |extension 25=ADCX | + | | extension 8 = SSE4.2 |
− | |extension 26=PREFETCHW | + | | extension 9 = POPCNT |
− | |extension 27=CLFLUSHOPT | + | | extension 10 = AVX |
− | |extension 28=XSAVE | + | | extension 11 = AVX2 |
− | |extension 29=SGX | + | | extension 12 = AES |
− | |extension 30=MPX | + | | extension 13 = PCLMUL |
− | |l1i=32 KiB | + | | extension 14 = FSGSBASE |
− | |l1i per=core | + | | extension 15 = RDRND |
− | |l1i desc=8-way set associative | + | | extension 16 = FMA3 |
− | |l1d=32 KiB | + | | extension 17 = F16C |
− | |l1d per=core | + | | extension 18 = BMI |
− | |l1d desc=8-way set associative | + | | extension 19 = BMI2 |
− | |l2=256 KiB | + | | extension 20 = VT-x |
− | |l2 per=core | + | | extension 21 = VT-d |
− | |l2 desc=4-way set associative | + | | extension 22 = TXT |
− | |l3=2 MiB | + | | extension 23 = TSX |
− | |l3 per=core | + | | extension 24 = RDSEED |
− | |l3 desc=Up to 16-way set associative | + | | extension 25 = ADCX |
− | | | + | | extension 26 = PREFETCHW |
− | | | + | | extension 27 = CLFLUSHOPT |
− | | | + | | extension 28 = XSAVE |
− | |core name=Kaby Lake Y | + | | extension 29 = SGX |
− | |core name 2=Kaby Lake U | + | | extension 30 = MPX |
− | |core name 3=Kaby Lake | + | | extension 31 = AVX-512 |
− | |core name 4=Kaby Lake | + | |
− | |core name 5=Kaby Lake | + | | cache = Yes |
− | |core name 6=Kaby Lake | + | | l1i = 32 KiB |
− | + | | l1i per = core | |
− | | | + | | l1i desc = 8-way set associative |
− | |predecessor=Skylake | + | | l1d = 32 KiB |
− | |predecessor link=intel/microarchitectures/skylake | + | | l1d per = core |
− | |successor=Coffee Lake | + | | l1d desc = 8-way set associative |
− | |successor link=intel/microarchitectures/coffee lake | + | | l2 = 256 KiB |
− | |successor 2= | + | | l2 per = core |
− | |successor 2 link=intel/microarchitectures/ | + | | l2 desc = 4-way set associative |
+ | | l3 = 2 MiB | ||
+ | | l3 per = core | ||
+ | | l3 desc = Up to 16-way set associative | ||
+ | | l4 = 64 MiB | ||
+ | | l4 per = package | ||
+ | | l4 desc = on Iris Plus GPUs only | ||
+ | |||
+ | | core names = Yes | ||
+ | | core name = Kaby Lake Y | ||
+ | | core name 2 = Kaby Lake U | ||
+ | | core name 3 = Kaby Lake H | ||
+ | | core name 4 = Kaby Lake S | ||
+ | | core name 5 = Kaby Lake X | ||
+ | | core name 6 = Kaby Lake W | ||
+ | |||
+ | | succession = Yes | ||
+ | | predecessor = Skylake | ||
+ | | predecessor link = intel/microarchitectures/skylake | ||
+ | | successor = Coffee Lake | ||
+ | | successor link = intel/microarchitectures/coffee lake | ||
+ | | successor 2 = Cannonlake | ||
+ | | successor 2 link = intel/microarchitectures/cannonlake | ||
}} | }} | ||
− | [[File:7th Gen Core-i7-badge.png|thumb|right| | + | [[File:7th Gen Core-i7-badge.png|thumb|right|250px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]] |
− | '''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\| | + | '''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops, servers, and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\|Cannonlake}} was originally set to replace {{\\|Skylake}} as the next microarchitecture using a [[10 nm process]], however Intel later revised their roadmap to include Kaby Lake (with Cannonlake being pushed back to [[2017]]). |
− | For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For | + | For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}, {{intel|Xeon E5|Xeon E5 v6}}, and {{intel|Xeon E7|Xeon E7 v6}}. |
== Codenames == | == Codenames == | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Core !! Abbrev !! | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
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− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake Y|l=core}} || KBL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks |
|- | |- | ||
− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake U|l=core}} || KBL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
|- | |- | ||
− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake H|l=core}} || KBL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations |
|- | |- | ||
− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake S|l=core}} || KBL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis |
|- | |- | ||
− | | {{intel|Kaby Lake X|l=core}} || KBL-X | + | | {{intel|Kaby Lake X|l=core}} || KBL-X || Extreme Performance || || High-end desktops & enthusiasts market |
|- | |- | ||
− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake W|l=core}} || KBL-W || Workstation || || Workstations |
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|} | |} | ||
== Release Dates == | == Release Dates == | ||
− | Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017 | + | Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017. |
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== Process Technology == | == Process Technology == | ||
− | { | + | {{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}} |
− | + | Kaby Lake uses a modified and improved [[14 nm process]] used for the Broadwell microarchitecture (And {{\\|Skylake}}). Intel calls the process "14nm+". Intel claims the new process has improved [[transistor]] channel strain. These changes allowed Intel to increase the maximum frequencies of all models by around 100 to 300 [[megahertz]] which gives many [[single-thread]] applications a modest performance increase. Note that beyond that not much else is known about the changes that were done to the actual transistor shape and size. | |
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− | Kaby Lake uses a modified and improved [[14 nm process]] used for the Broadwell microarchitecture (And {{\\|Skylake}}). Intel calls the | ||
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== Compatibility == | == Compatibility == | ||
− | There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. | + | There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. Microsoft announced that only [[Windows 10]] will have support for Kaby Lake. [[Linux]] added initial support for Kaby Lake starting with Linux Kernel 4.5. |
{| class="wikitable" | {| class="wikitable" | ||
! Vendor !! OS !! Version !! Notes | ! Vendor !! OS !! Version !! Notes | ||
|- | |- | ||
− | | rowspan="3" | | + | | rowspan="3" | Microsoft || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support |
|- | |- | ||
| style="background-color: #ffdad6;" | Windows 8 || No Support | | style="background-color: #ffdad6;" | Windows 8 || No Support | ||
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|- | |- | ||
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code> | | [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code> | ||
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|} | |} | ||
== Architecture == | == Architecture == | ||
− | + | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake. | |
− | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake | ||
=== Key changes from {{\\|Skylake}} === | === Key changes from {{\\|Skylake}} === | ||
− | |||
* Same IPC as Skylake (i.e. performance/[[MHz]] is unchanged) | * Same IPC as Skylake (i.e. performance/[[MHz]] is unchanged) | ||
+ | * Enhanced "14nm+" process results in ~15% higher frequency (100 to 300 MHz increase across the board) | ||
* 10x performance/[[Watt]] over {{\\|Nehalem}} (Up from 8x) | * 10x performance/[[Watt]] over {{\\|Nehalem}} (Up from 8x) | ||
+ | * {{intel|LGA-1151|Socket 1151}} now uses {{intel|Union Point}} (200-series chipset) (See [[#Sockets.2FPlatform|§ Sockets]]) | ||
* [[intel/microarchitectures/skylake#.22Speed_Shift.22_.28new_power_management.29|SkyLake's Speed Shift]] implementation is significantly improved, cutting responsiveness by as much as 66% (down to just ~10-15ms to peak frequency). | * [[intel/microarchitectures/skylake#.22Speed_Shift.22_.28new_power_management.29|SkyLake's Speed Shift]] implementation is significantly improved, cutting responsiveness by as much as 66% (down to just ~10-15ms to peak frequency). | ||
− | + | * Support for {{intel|Optane}} Technology | |
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* Interfaces | * Interfaces | ||
** [[Embedded DisplayPort]] ([[eDP]]) now supports eDP Standard 1.4 (From 1.3 in Skylake) | ** [[Embedded DisplayPort]] ([[eDP]]) now supports eDP Standard 1.4 (From 1.3 in Skylake) | ||
− | * | + | * Gen 9.5 GPUs |
− | |||
** New native hardware support for 4K HEVC/VP9 (See [[#Graphics|§ Graphics]]) | ** New native hardware support for 4K HEVC/VP9 (See [[#Graphics|§ Graphics]]) | ||
** {{intel|HD Graphics 510}} '''→''' {{intel|HD Graphics 610}} (12 Execution Units, no change) | ** {{intel|HD Graphics 510}} '''→''' {{intel|HD Graphics 610}} (12 Execution Units, no change) | ||
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* Families | * Families | ||
− | ** {{intel|Core i3}} processors dropped support for ECC memory | + | ** {{intel|Core i3}} processors dropped support for ECC memory |
** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.) | ||
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=== Block Diagram === | === Block Diagram === | ||
− | + | [[File:skylake block diagram.svg]] | |
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− | [[File:skylake block diagram.svg | ||
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=== Memory Hierarchy === | === Memory Hierarchy === | ||
The overall memory structure is identical to {{\\|Skylake}}. | The overall memory structure is identical to {{\\|Skylake}}. | ||
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* Cache | * Cache | ||
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** L1I Cache: | ** L1I Cache: | ||
− | *** 32 | + | *** 32 KiB 8-way set associative |
− | **** | + | **** 64 B line size |
+ | **** Write-back policy | ||
**** shared by the two threads, per core | **** shared by the two threads, per core | ||
** L1D Cache: | ** L1D Cache: | ||
− | *** 32 KiB | + | *** 32 KiB 8-way set associative |
− | *** | + | *** 64 B line size |
*** shared by the two threads, per core | *** shared by the two threads, per core | ||
− | *** 4 cycles for fastest load-to-use | + | *** 4 cycles for fastest load-to-use |
− | + | *** 64 Bytes/cycle load bandwidth | |
− | *** 64 | + | *** 32 Bytes/cycle store bandwidth |
− | *** 32 | ||
*** Write-back policy | *** Write-back policy | ||
** L2 Cache: | ** L2 Cache: | ||
− | *** | + | *** unified, 256 KiB 4-way set associative |
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*** 12 cycles for fastest load-to-use | *** 12 cycles for fastest load-to-use | ||
− | *** | + | *** 64B/cycle bandwidth to L1$ |
*** Write-back policy | *** Write-back policy | ||
− | ** L3 Cache | + | ** L3 Cache: |
− | *** Up to 2 MiB Per core, shared across all cores | + | *** Up to 2 MiB Per core, shared across all cores. |
*** Up to 16-way set associative | *** Up to 16-way set associative | ||
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*** Write-back policy | *** Write-back policy | ||
− | ** | + | ** L4 Cache: |
− | + | *** 64 MiB | |
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− | *** 64 MiB | ||
*** Per package | *** Per package | ||
− | *** Only on the Iris | + | *** Only on the Iris Plus GPUs |
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− | Kaby Lake TLB consists of dedicated | + | Kaby Lake TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB. |
* TLBs: | * TLBs: | ||
** ITLB | ** ITLB | ||
*** 4 KiB page translations: | *** 4 KiB page translations: | ||
**** 128 entries; 8-way set associative | **** 128 entries; 8-way set associative | ||
− | **** dynamic | + | **** dynamic partition; divided between the two threads |
*** 2 MiB / 4 MiB page translations: | *** 2 MiB / 4 MiB page translations: | ||
− | **** 8 entries | + | **** 8 entries; fully associative |
**** Duplicated for each thread | **** Duplicated for each thread | ||
** DTLB | ** DTLB | ||
*** 4 KiB page translations: | *** 4 KiB page translations: | ||
**** 64 entries; 4-way set associative | **** 64 entries; 4-way set associative | ||
− | **** fixed partition | + | **** fixed partition; divided between the two threads |
*** 2 MiB / 4 MiB page translations: | *** 2 MiB / 4 MiB page translations: | ||
**** 32 entries; 4-way set associative | **** 32 entries; 4-way set associative | ||
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**** 16 entries; 4-way set associative | **** 16 entries; 4-way set associative | ||
**** fixed partition | **** fixed partition | ||
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− | + | === Graphics === | |
− | + | Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, an [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Kaby Lake's biggest enhancement is the addition of native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit). | |
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− | == Graphics == | ||
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− | Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, | ||
{| class="wikitable tc2 tc3" | {| class="wikitable tc2 tc3" | ||
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| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | ||
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− | | {{intel|HD Graphics 610}} || 12 || GT1 | | + | | {{intel|HD Graphics 610}} || 12 || GT1 || S, U || - || rowspan="7" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="7" style="text-align: center;" | '''12''' || rowspan="7" style="text-align: center;" | '''N/A''' || rowspan="7" style="text-align: center;" | '''5.1''' || rowspan="7" style="text-align: center;" | '''4.4''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;" | '''2.0''' || rowspan="7" style="text-align: center;" | '''1.2''' |
|- | |- | ||
− | | {{intel|HD Graphics 615}} || 24 || GT2|| | + | | {{intel|HD Graphics 615}} || 24 || GT2|| Y || - |
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− | | {{intel|HD Graphics 620}} || 24 || GT2 || | + | | {{intel|HD Graphics 620}} || 24 || GT2 || U || - |
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− | | {{intel|HD Graphics 630}} || 24 || GT2 || | + | | {{intel|HD Graphics 630}} || 24 || GT2 || S, H || - |
|- | |- | ||
− | | {{intel|HD Graphics P630}} || 24 || GT2 || | + | | {{intel|HD Graphics P630}} || 24 || GT2 || H || - |
|- | |- | ||
− | | {{intel|Iris Plus Graphics 640}} || 48 || GT3e|| | + | | {{intel|Iris Plus Graphics 640}} || 48 || GT3e|| U || 64 MiB |
|- | |- | ||
− | | {{intel|Iris Plus Graphics 650}} || 48 || GT3e || | + | | {{intel|Iris Plus Graphics 650}} || 48 || GT3e || U || 64 MiB |
|} | |} | ||
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{{kaby lake hardware accelerated video table}} | {{kaby lake hardware accelerated video table}} | ||
− | == Sockets/Platform == | + | === Sockets/Platform === |
− | {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|U|l=core}} are single-chip solutions. {{intel|Kaby Lake Y|Y|l=core}} chips utilize a 2 | + | {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|U|l=core}} are single-chip solutions. {{intel|Kaby Lake Y|Y|l=core}} chips utilize a 2 dice multi-chip package (MCP) whereas the {{intel|Kaby Lake U|l=core}}'s are either 2 or 3 dice MCP configuration. The 3 dice chip configuration are for the Iris [[IGP]]s which incorporate an on-package cache (OPC) in addition to the hub. {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|H|l=core}} are a two-chip solution linked together via Intel's standard [[DMI 3.0]] bus interface. Only {{intel|Kaby Lake S|l=core}} (used on mainstream desktop processors) are not soldered onto the [[motherboard]] and can be interchanged/replaced. |
− | {| class="wikitable | + | {| class="wikitable tc3 tc5 tc6" |
|- | |- | ||
− | + | ! Core !! Socket !! Permanent !! Platform !! Chipset !! Bus | |
|- | |- | ||
− | + | | {{intel|Kaby Lake Y|l=core}} || {{intel|BGA-1515}} || Yes || 1-chip || rowspan="2" | N/A || rowspan="2" | OPI | |
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− | + | | {{intel|Kaby Lake U|l=core}} || {{intel|BGA-1356}} || Yes || 1-chip | |
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− | | {{intel|Kaby Lake H|l=core}} || | + | | {{intel|Kaby Lake H|l=core}} || {{intel|BGA-1440}} || Yes || 2-chip || {{intel|Sunrise Point}} || rowspan="2" | [[DMI 3.0]] |
|- | |- | ||
− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake S|l=core}} || {{intel|LGA-1151}} || No || 2-chip || {{intel|Union Point}} |
|- | |- | ||
− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake X|l=core}} |
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− | | {{intel|Kaby Lake | + | | {{intel|Kaby Lake W|l=core}} |
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|} | |} | ||
== Die == | == Die == | ||
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=== Dual-Core === | === Dual-Core === | ||
− | + | [[Dual Core]] Kaby Lake Processor: | |
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− | : [[File:kaby lake | + | : [[File:kaby lake (dual core).png|850px]] |
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− | + | : [[File:kaby lake (dual core) (annotated).png|850px]] | |
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− | File: | ||
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== All Kaby Lake Chips == | == All Kaby Lake Chips == | ||
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{{comp table start}} | {{comp table start}} | ||
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23"> | <table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23"> | ||
− | <tr class="comptable-header"><th> </th><th colspan=" | + | <tr class="comptable-header"><th> </th><th colspan="23">Kaby Lake Chips</th></tr> |
− | <tr class="comptable-header"><th> </th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan=" | + | <tr class="comptable-header"><th> </th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr> |
− | <tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number"> | + | <tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">C</th><th data-sort-type="number">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr> |
− | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan=" | + | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="23">[[Uniprocessors]]</th></tr> |
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1 | + | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] |
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|?full page name | |?full page name | ||
|?model number | |?model number | ||
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|?integrated gpu base frequency | |?integrated gpu base frequency | ||
|?integrated gpu max frequency | |?integrated gpu max frequency | ||
− | + | |?has intel turbo boost technology 2.0 | |
− | |?has intel turbo boost technology | ||
|?has simultaneous multithreading | |?has simultaneous multithreading | ||
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|?has advanced vector extensions 2 | |?has advanced vector extensions 2 | ||
|?has intel trusted execution technology | |?has intel trusted execution technology | ||
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|sort=microprocessor family, model number | |sort=microprocessor family, model number | ||
|order=asc,asc | |order=asc,asc | ||
− | |userparam= | + | |userparam=25:19 |
|mainlabel=- | |mainlabel=- | ||
|limit=100 | |limit=100 | ||
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== Documents == | == Documents == | ||
− | + | * [[:File:7th Generation Intel® Core™ Processor Product Brief.pdf|7th Generation Intel® Core™ Processor Product Brief]] | |
− | + | * [[:File:7th Generation Intel® Core™ Processor Y-Series and U-Series Product Brief.pdf|7th Generation Intel® Core™ Processor Y-Series and U-Series Product Brief]] | |
− | * [[:File:7th Generation Intel® Core™ Processor Product Brief.pdf|7th Generation | + | * [[:File:7th Gen Intel® Core™ Processor Family Fact Sheet.pdf|7th Gen Intel® Core™ Processor Family Fact Sheet]] |
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− | * [[:File:7th Generation Intel® Core™ Processor Y-Series and U-Series Product Brief.pdf|7th Generation | ||
− | * [[:File:7th Gen Intel® Core™ Processor Family Fact Sheet.pdf|7th Gen | ||
* [[:File:7th-generation-core-processor-deskop-iot-platform-brief.pdf|7th Generation Intel Core Processor-Based Platforms for Internet of Things (IoT) Solutions Platform brief]] | * [[:File:7th-generation-core-processor-deskop-iot-platform-brief.pdf|7th Generation Intel Core Processor-Based Platforms for Internet of Things (IoT) Solutions Platform brief]] | ||
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== See also == | == See also == | ||
* {{amd|microarchitectures/zen|AMD's Zen}} | * {{amd|microarchitectures/zen|AMD's Zen}} |
Facts about "Kaby Lake - Microarchitectures - Intel"
codename | Kaby Lake + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/kaby lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Kaby Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |