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| phase-out = April, 2013 | | phase-out = April, 2013 | ||
| process = 22 nm | | process = 22 nm | ||
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| succession = Yes | | succession = Yes | ||
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| successor link = intel/microarchitectures/haswell | | successor link = intel/microarchitectures/haswell | ||
}} | }} | ||
− | '''Ivy Bridge''' ('''IVB''') was [[Intel]]'s [[microarchitecture]] based on the [[22 nm process]] for desktops and servers. Ivy Bridge was introduced in 2011 as a [[process shrink]] of {{\\|Sandy Bridge}} which introduced a number | + | '''Ivy Bridge''' ('''IVB''') was [[Intel]]'s [[microarchitecture]] based on the [[22 nm process]] for desktops and servers. Ivy Bridge was introduced in 2011 as a [[process shrink]] of {{\\|Sandy Bridge}} which introduced a number enhancements. Ivy Bridge became Intel's first microarchitecture to use [[tri-gate transistor]]s for their commercial products. |
For desktop and mobile, Ivy Bridge is branded as 3rd Generation Intel {{intel|Core}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v2}}, {{intel|Xeon E5|Xeon E5 v2}}, and {{intel|Xeon E7|Xeon E7 v2}}. | For desktop and mobile, Ivy Bridge is branded as 3rd Generation Intel {{intel|Core}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v2}}, {{intel|Xeon E5|Xeon E5 v2}}, and {{intel|Xeon E7|Xeon E7 v2}}. | ||
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| Fab 28 || Kiryat Gat, Israel | | Fab 28 || Kiryat Gat, Israel | ||
|} | |} | ||
− | Ivy Bridge is designed to be manufactured using [[22 nm]] Tri-gate [[FinFET]] transistors. This is Intel's first generation of [[FinFET]]. This correlates to 8 nm Fin width and a | + | Ivy Bridge is designed to be manufactured using [[22 nm]] Tri-gate [[FinFET]] transistors. This is Intel's first generation of [[FinFET]]. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.1080 µm² and 0.092 µm² for high performance and high density respectively. |
[[Scaling]]: | [[Scaling]]: | ||
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=== Key changes from {{\\|Sandy Bridge}} === | === Key changes from {{\\|Sandy Bridge}} === | ||
{{empty section}} | {{empty section}} | ||
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=== Block Diagram === | === Block Diagram === | ||
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== Die == | == Die == | ||
===Quad-core Ivy Bridge die=== | ===Quad-core Ivy Bridge die=== | ||
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* 1,480,000,000 transistors | * 1,480,000,000 transistors | ||
* 160 mm<sup>2</sup> | * 160 mm<sup>2</sup> | ||
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: [[File:ivy bridge die (quad-core) (annotated).png|850px]] | : [[File:ivy bridge die (quad-core) (annotated).png|850px]] | ||
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===Hexa-core Ivy Bridge Die=== | ===Hexa-core Ivy Bridge Die=== | ||
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:[[File:ivy bridge (hexa-core) die shot (annotated).png|650px]] | :[[File:ivy bridge (hexa-core) die shot (annotated).png|650px]] | ||
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* 540 mm² | * 540 mm² | ||
* 4,310,000,000 transistors | * 4,310,000,000 transistors | ||
+ | * [[22 nm process]] | ||
* 15 CPU cores | * 15 CPU cores | ||
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[[File:intel xeon e7 v2.jpg|850px]] | [[File:intel xeon e7 v2.jpg|850px]] | ||
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created and tagged accordingly. | created and tagged accordingly. | ||
− | Missing a chip? please dump its name here: | + | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips |
--> | --> | ||
− | + | <table class="wikitable sortable"> | |
− | <table class=" | + | <tr><th colspan="12" style="background:#D6D6FF;">Ivy Bridge Chips</th></tr> |
− | <tr | + | <tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr> |
− | <tr | + | <tr><th>Model</th><th>µarch</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr> |
− | + | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ivy Bridge]] | |
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ivy Bridge | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
+ | |?microarchitecture | ||
+ | |?platform | ||
+ | |?core name | ||
|?first launched | |?first launched | ||
− | |? | + | |?sdp |
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|?tdp | |?tdp | ||
− | |?base frequency | + | |?base frequency |
− | + | |?max memory | |
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− | |?max memory | ||
|?integrated gpu | |?integrated gpu | ||
|?integrated gpu base frequency | |?integrated gpu base frequency | ||
|?integrated gpu max frequency | |?integrated gpu max frequency | ||
|format=template | |format=template | ||
− | |template=proc table | + | |template=proc table 2 |
− | + | |userparam=13 | |
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− | |userparam= | ||
|mainlabel=- | |mainlabel=- | ||
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}} | }} | ||
− | {{ | + | <tr><th colspan="12">Count: {{#ask:[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Ivy Bridge]]|format=count}}</th></tr> |
</table> | </table> | ||
− |
Facts about "Ivy Bridge - Microarchitectures - Intel"
codename | Ivy Bridge + |
designer | Intel + |
first launched | May 4, 2011 + |
full page name | intel/microarchitectures/ivy bridge (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ivy Bridge + |
phase-out | April 2013 + |
process | 22 nm (0.022 μm, 2.2e-5 mm) + |