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|extension 11=PCLMUL | |extension 11=PCLMUL | ||
|extension 12=RDRND | |extension 12=RDRND | ||
− | |extension 13 | + | |extension 13=SHA |
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|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=Core | |l1i per=Core | ||
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|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|core name=Gemini Lake | |core name=Gemini Lake | ||
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|predecessor=Goldmont | |predecessor=Goldmont | ||
|predecessor link=intel/microarchitectures/goldmont | |predecessor link=intel/microarchitectures/goldmont | ||
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|- | |- | ||
| {{intel|Gemini Lake}} || GLK || Low-power PCs, tablets, and embedded devices | | {{intel|Gemini Lake}} || GLK || Low-power PCs, tablets, and embedded devices | ||
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|} | |} | ||
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ||
|- | |- | ||
− | | rowspan="2" | {{intel|Gemini Lake|l=core}} || 0 || | + | | rowspan="2" | {{intel|Gemini Lake|l=core}} || 0 || 6 || 7 || 10 |
|- | |- | ||
− | | colspan="4" | Family 6 Model | + | | colspan="4" | Family 6 Model 10 |
|} | |} | ||
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** Larger ROB | ** Larger ROB | ||
** Execution Units | ** Execution Units | ||
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** Wider integer execution unit | ** Wider integer execution unit | ||
** New dedicated JEU port | ** New dedicated JEU port | ||
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*** 2 MiB 16-way set associative, 64 B line size | *** 2 MiB 16-way set associative, 64 B line size | ||
*** Per 2 cores | *** Per 2 cores | ||
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** L3 Cache: | ** L3 Cache: | ||
*** No level 3 cache | *** No level 3 cache |
Facts about "Goldmont Plus - Microarchitectures - Intel"
codename | Goldmont Plus + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | December 11, 2017 + |
full page name | intel/microarchitectures/goldmont plus + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont Plus + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |