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Latest revision Your text
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|extension 11=PCLMUL
 
|extension 11=PCLMUL
 
|extension 12=RDRND
 
|extension 12=RDRND
|extension 13=XSAVE
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|extension 13=SHA
|extension 14=XSAVEOPT
 
|extension 15=FSGSBASE
 
|extension 16=PTWRITE
 
|extension 17=RDPID
 
|extension 18=SGX
 
|extension 19=UMIP
 
|extension 20=SHA
 
 
|l1i=32 KiB
 
|l1i=32 KiB
 
|l1i per=Core
 
|l1i per=Core
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|l1d per=Core
 
|l1d per=Core
 
|l1d desc=6-way set associative
 
|l1d desc=6-way set associative
|l2=4 MiB
+
|l2=2 MiB
|l2 per=4 Cores
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|l2 per=2 Cores
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|core name=Gemini Lake
 
|core name=Gemini Lake
|core name 2=Gemini Lake Refresh
 
 
|predecessor=Goldmont
 
|predecessor=Goldmont
 
|predecessor link=intel/microarchitectures/goldmont
 
|predecessor link=intel/microarchitectures/goldmont
|successor=Tremont
 
|successor link=intel/microarchitectures/tremont
 
 
}}
 
}}
'''Goldmont Plus''' ('''GLM+''', '''GLP''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium Silver}}, and {{intel|Celeron}} families.
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'''Goldmont Plus''' ('''GLM+''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium (2009)|Pentium}}, and {{intel|Celeron}} families.
  
 
== Codenames ==
 
== Codenames ==
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|-
 
|-
 
| {{intel|Gemini Lake}} || GLK || Low-power PCs, tablets, and embedded devices
 
| {{intel|Gemini Lake}} || GLK || Low-power PCs, tablets, and embedded devices
|-
 
| {{intel|Gemini Lake Refresh}} || GLK || Low-power PCs, tablets, and embedded devices
 
 
|}
 
|}
  
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== Release Dates ==
 
== Release Dates ==
Goldmont Plus processors were launched on December 11, 2017 for desktop, mobile and embedded devices. Server-based parts are expected to be introduced in 2018.
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Goldmont Plus processors were launched on December 11 2017 for desktop, mobile and embedded devices. Server-based parts are expected to be introduced in 2018.
 
 
== Technology ==
 
Goldmont Plus, like its predecessor, is manufactured on Intel's original [[14 nm process]] (as opposed to 14nm+ or 14nm++).
 
  
 
== Compiler support ==
 
== Compiler support ==
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
|-
 
|-
| rowspan="2" | {{intel|Gemini Lake|l=core}} || 0 || 0x6 || 0x7 || 0xA
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| rowspan="2" | {{intel|Gemini Lake|l=core}} || 0 || ? || ? || ?
 
|-
 
|-
| colspan="4" | Family 6 Model 122
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| colspan="4" | Family 6 Model ?
 
|}
 
|}
  
 
== Architecture ==
 
== Architecture ==
Despite the name "Goldmont Plus", this microarchitecture is a very large implementational jump from "Goldmont" with improvements across the board from the caches to a wider pipeline.
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{{future information}}
 
=== Key changes from {{\\|Goldmont}} ===
 
=== Key changes from {{\\|Goldmont}} ===
* Core
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* 4-way decode (from 3-way)<ref>https://patchwork.kernel.org/patch/9836747/</ref>
** Front End
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* VP9 10-bit Profile2 hardware decoding
*** Enhanced branch prediction
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* Integrated native HDMI 2.0 controller
** Back End
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* Integrated Intel Wireless-AC(Wi-Fi/BT CNVi)
*** 4-way allocation (from 3)
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* 4 MiB L2 cache per duplex (Up from 2 MiB)
*** 4-way retire (from 3)
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** Larger reservation station
 
** Larger ROB
 
** Execution Units
 
*** POPF latency reduced from ~80 to ~40 cycles
 
*** Vector divisions and square roots are faster
 
*** AES operations: latency reduced from 6 to 4 cycles, throughput increased to 1 op/cycle
 
*** SHL, SHR, SAR, ROL and ROR with counter in CL: latency reduced from 2 to 1
 
** Wider integer execution unit
 
** New dedicated JEU port
 
*** Supports faster branch redirection.
 
** Radix-1024 floating point divider for fast scalar/packed single, double and extended precision floating point divides
 
** Improved {{x86|AES}} instruction latency and throughput.
 
** Memory Subsystem
 
*** 64 KiB 2nd level pre-decode cache (from 16 KiB)
 
*** Larger load buffer
 
*** Larger store buffer
 
*** Improved store-to-load forwarding latency store data from register
 
*** New STLB
 
**** Shared by instruction and data
 
*** Paging Cache Enhancements (PxE/ePxE caches)
 
* Cache
 
** 4 MiB L2 per quad core module (Up from 1 MiB per duplex)
 
 
* Graphics
 
* Graphics
** {{intel|Gen 9.5|l=arch}} execution engines, {{intel|Gen 10|l=arch}} Display
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** {{intel|Gen 9.5|l=arch}} GPUs
* New Integration
 
** {{intel|CNVi|Integrated Connectivity CNVi}}
 
*** Supports up to Wireless-AC CRFs
 
** HDMI 2.0 (from 1.4a)
 
*** 2160p (4K) @ 60 Hz (from 24 Hz)
 
** VP9 10-bit Profile2 hardware decoding
 
 
** HD Graphics 50x '''→''' UHD Graphics 60x
 
** HD Graphics 50x '''→''' UHD Graphics 60x
 
*** {{intel|HD Graphics 505}} '''→''' {{intel|UHD Graphics 605}} (Pentium Silver J/N 5xxx with 18EU)
 
*** {{intel|HD Graphics 505}} '''→''' {{intel|UHD Graphics 605}} (Pentium Silver J/N 5xxx with 18EU)
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* {{x86|SGX1|<code>SGX1</code>}} - Software Guard Extensions, Version 1
 
* {{x86|SGX1|<code>SGX1</code>}} - Software Guard Extensions, Version 1
* {{x86|UMIP|<code>UMIP</code>}} - User-mode instruction prevention
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* UMIP
* {{x86|PTWRITE|<code>PTWRITE</code>}} - Trace logger write user data
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* PTWRITE
* {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID
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* RDPID
  
 
=== Block Diagram ===
 
=== Block Diagram ===
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*** 2 MiB 16-way set associative, 64 B line size
 
*** 2 MiB 16-way set associative, 64 B line size
 
*** Per 2 cores
 
*** Per 2 cores
*** 32B/cycle, 19 cycle latency
 
 
** L3 Cache:
 
** L3 Cache:
 
*** No level 3 cache
 
*** No level 3 cache
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=== Multithreading ===
 
=== Multithreading ===
 
Goldmont Plus, like {{\\|Goldmont}} has no support for Intel Hyper-Threading Technology.
 
Goldmont Plus, like {{\\|Goldmont}} has no support for Intel Hyper-Threading Technology.
 
== New Integration ==
 
=== Integrated Connectivity (CNVi) ===
 
{{main|intel/cnvi|l1=CNVi}}
 
A new integration to Goldmont Plus is '''Integrated Connectivity''' ('''CNVi''') which is an architecture for wireless connectivity devices. CNVi attempts to simplify vendors bill of material (BOM) size and cost by integrating the majority of the expensive functionality found in an RF chip. The only thing not integrated are the actual analog and RF functions which come from a relatively inexpensive companion RF (CRF) module connected via a standard [[M.2]] card and provides support for things such as [[IEEE 802.11ac]].
 
  
 
== All Goldmont Plus Chips ==
 
== All Goldmont Plus Chips ==

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codenameGoldmont Plus +
core count2 + and 4 +
designerIntel +
first launchedDecember 11, 2017 +
full page nameintel/microarchitectures/goldmont plus +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGoldmont Plus +
process14 nm (0.014 μm, 1.4e-5 mm) +