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|extension 11=PCLMUL | |extension 11=PCLMUL | ||
|extension 12=RDRND | |extension 12=RDRND | ||
− | |extension 13 | + | |extension 13=SHA |
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|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=Core | |l1i per=Core | ||
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|l1d per=Core | |l1d per=Core | ||
|l1d desc=6-way set associative | |l1d desc=6-way set associative | ||
− | |l2= | + | |l2=2 MiB |
− | |l2 per= | + | |l2 per=2 Cores |
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|core name=Gemini Lake | |core name=Gemini Lake | ||
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|predecessor=Goldmont | |predecessor=Goldmont | ||
|predecessor link=intel/microarchitectures/goldmont | |predecessor link=intel/microarchitectures/goldmont | ||
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}} | }} | ||
− | '''Goldmont Plus''' ('''GLM+ | + | '''Goldmont Plus''' ('''GLM+''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium (2009)|Pentium}}, and {{intel|Celeron}} families. |
== Codenames == | == Codenames == | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! | + | ! Platform !! Core !! Target |
|- | |- | ||
− | | {{intel|Gemini Lake}} | | + | | {{intel|Gemini Lake}} || {{intel|Gemini Lake|l=core}} || Entry-level PCs, tablets, embedded devices, storage |
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− | | {{intel|Gemini Lake | ||
|} | |} | ||
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== Release Dates == | == Release Dates == | ||
− | Goldmont Plus processors were launched on December 11 | + | Goldmont Plus processors were launched on December 11 2017 for desktop, mobile and embedded devices. Server-based parts are expected to be introduced in 2018. |
− | == | + | == Architecture == |
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{{future information}} | {{future information}} | ||
− | {| | + | === Key changes from {{\\|Goldmont}} === |
− | + | * 4-way decode (from 3-way)<ref>https://patchwork.kernel.org/patch/9836747/</ref> | |
− | + | * VP9 10-bit Profile2 hardware decoding | |
− | + | * Integrated native HDMI 2.0 controller | |
− | + | * Integrated Intel Wireless-AC(Wi-Fi/BT CNVi) | |
− | + | * 4 MiB L2 cache per duplex (Up from 2 MiB) | |
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* Graphics | * Graphics | ||
− | ** {{intel|Gen 9.5|l=arch}} | + | ** {{intel|Gen 9.5|l=arch}} GPUs |
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** HD Graphics 50x '''→''' UHD Graphics 60x | ** HD Graphics 50x '''→''' UHD Graphics 60x | ||
*** {{intel|HD Graphics 505}} '''→''' {{intel|UHD Graphics 605}} (Pentium Silver J/N 5xxx with 18EU) | *** {{intel|HD Graphics 505}} '''→''' {{intel|UHD Graphics 605}} (Pentium Silver J/N 5xxx with 18EU) | ||
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* {{x86|SGX1|<code>SGX1</code>}} - Software Guard Extensions, Version 1 | * {{x86|SGX1|<code>SGX1</code>}} - Software Guard Extensions, Version 1 | ||
− | * | + | * UMIP |
− | * | + | * PTWRITE |
− | * | + | * RDPID |
=== Block Diagram === | === Block Diagram === | ||
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*** Per core | *** Per core | ||
** L2 Cache: | ** L2 Cache: | ||
− | *** | + | *** 4 MiB 16-way set associative, 64 B line size |
*** Per 2 cores | *** Per 2 cores | ||
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** L3 Cache: | ** L3 Cache: | ||
*** No level 3 cache | *** No level 3 cache | ||
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=== Multithreading === | === Multithreading === | ||
Goldmont Plus, like {{\\|Goldmont}} has no support for Intel Hyper-Threading Technology. | Goldmont Plus, like {{\\|Goldmont}} has no support for Intel Hyper-Threading Technology. | ||
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== All Goldmont Plus Chips == | == All Goldmont Plus Chips == |
Facts about "Goldmont Plus - Microarchitectures - Intel"
codename | Goldmont Plus + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | December 11, 2017 + |
full page name | intel/microarchitectures/goldmont plus + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont Plus + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |