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| successor link = intel/microarchitectures/gen10 | | successor link = intel/microarchitectures/gen10 | ||
}} | }} | ||
− | '''Gen9.5''' (''Generation 9.5'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Kaby Lake | + | '''Gen9.5''' (''Generation 9.5'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Kaby Lake}}-based microprocessors. Gen9.5 is the successor to {{\\|Gen9}} used by {{\\|Skylake}} and introduces a number of light enhancements. |
== Codenames == | == Codenames == | ||
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| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | ||
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− | | {{intel| | + | | {{intel|HD Graphics 610}} || 12 || GT1 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake U|U}} || - || rowspan="7" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="7" style="text-align: center;" | '''12''' || rowspan="7" style="text-align: center;" | '''N/A''' || rowspan="7" style="text-align: center;" | '''5.1''' || rowspan="7" style="text-align: center;" | '''4.4''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;" colspan="2" | '''2.0''' |
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| {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || - | | {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || - | ||
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| {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || - | | {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || - | ||
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| {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || - | | {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || - | ||
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| {{intel|HD Graphics P630}} || 24 || GT2 || {{intel|Kaby Lake H|H}} || - | | {{intel|HD Graphics P630}} || 24 || GT2 || {{intel|Kaby Lake H|H}} || - | ||
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| {{intel|HD Graphics 620}} || KBL-U 2+2 || H0 || C0/B0 || 0x5916 || 0x2 | | {{intel|HD Graphics 620}} || KBL-U 2+2 || H0 || C0/B0 || 0x5916 || 0x2 | ||
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| rowspan="2" | {{intel|HD Graphics 630}} || KBL-S 4+2 || B0 || F0/C0 || 0x5912 || 0x4 | | rowspan="2" | {{intel|HD Graphics 630}} || KBL-S 4+2 || B0 || F0/C0 || 0x5912 || 0x4 | ||
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| KBL Halo 4+2 || || || 0x591B || | | KBL Halo 4+2 || || || 0x591B || | ||
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− | + | | {{intel|HD Graphics P630}} || KBL WKS 4+2 || || || 0x591D || | |
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− | | {{intel|HD Graphics P630}} || KBL WKS 4+2 | ||
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| {{intel|Iris Plus Graphics 640}} || KBL-U 2+3 || rowspan="2" | 48 || J1 || D1/B1 || 0x5926 || 0x6 | | {{intel|Iris Plus Graphics 640}} || KBL-U 2+3 || rowspan="2" | 48 || J1 || D1/B1 || 0x5926 || 0x6 | ||
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<references group=devID /> | <references group=devID /> | ||
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== Hardware Accelerated Video == | == Hardware Accelerated Video == | ||
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=== Key changes from {{\\|Gen9}} === | === Key changes from {{\\|Gen9}} === | ||
− | * Enhanced "14nm+" process (while CPU cores base frequency was | + | * Enhanced "14nm+" process (while CPU cores base frequency was increase, GPU speed remains unchanged) |
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* Display block | * Display block | ||
** [[Embedded DisplayPort]] ([[eDP]]) now supports eDP Standard 1.4 (From 1.3) | ** [[Embedded DisplayPort]] ([[eDP]]) now supports eDP Standard 1.4 (From 1.3) | ||
* Unslice | * Unslice | ||
** New native hardware support for 4K HEVC/VP9 | ** New native hardware support for 4K HEVC/VP9 | ||
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* DRM | * DRM | ||
** Support for Microsoft's PlayReady 3.0 | ** Support for Microsoft's PlayReady 3.0 | ||
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==== Preemption Granularity ==== | ==== Preemption Granularity ==== | ||
− | Preemption in Gen9 ({{\\|Skylake}}) was improved over Gen8 in a number of | + | Preemption in Gen9 ({{\\|Skylake}}) was improved over Gen8 in a number of way. Preemption is important for multi-tasking system and especially important for improving responsiveness of operations (i.e. the ability to stop and start operations quickly with minimal latency interruption for the end user). In {{\\|Broadwell}} ({{\\|Gen8}}) Intel added support for the ability to stop operations on object-level for 3D workloads such as on a triangle boundary (i.e. beginning of a triangle, between two triangles, between two lines or points) and be able to preempt and restore back to those operations. In Gen9 Intel added the ability to stop execution units on an instruction boundary and be able to restore them (previously such preemption was only possible at the boundary of a kernel - i.e. the entire kernel execution must take places before preemption was possible). Gen9 added support for thread-group (complete kernel execution) to mid-thread (instruction boundary) for compute workloads: |
Example of responsiveness (Source: IDF15) | Example of responsiveness (Source: IDF15) | ||
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=== Display === | === Display === | ||
− | The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/ | + | The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/207 rotations. |
[[File:gen9 display block.svg|650px]] | [[File:gen9 display block.svg|650px]] | ||
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* [[:File:intel-gfx-prm-osrc-kbl-vol02b-commandreference-enumerations.pdf|Volume 2b: Command Reference: Enumerations]] | * [[:File:intel-gfx-prm-osrc-kbl-vol02b-commandreference-enumerations.pdf|Volume 2b: Command Reference: Enumerations]] | ||
* [[:File:intel-gfx-prm-osrc-kbl-vol02c-commandreference-registers-part1.pdf|Volume 2c: Command Reference: Registers Part 1 – Registers A through L]] | * [[:File:intel-gfx-prm-osrc-kbl-vol02c-commandreference-registers-part1.pdf|Volume 2c: Command Reference: Registers Part 1 – Registers A through L]] | ||
− | * | + | * Volume 2c: Command Reference: Registers Part 2 – Registers M through Z (Manual Missing from Intel) |
* [[:File:intel-gfx-prm-osrc-kbl-vol02d-commandreference-structures.pdf|Volume 2d: Command Reference: Structures]] | * [[:File:intel-gfx-prm-osrc-kbl-vol02d-commandreference-structures.pdf|Volume 2d: Command Reference: Structures]] | ||
* [[:File:intel-gfx-prm-osrc-kbl-vol03-gpu overview.pdf|Volume 3: GPU Overview]] | * [[:File:intel-gfx-prm-osrc-kbl-vol03-gpu overview.pdf|Volume 3: GPU Overview]] |
Facts about "Gen9.5 - Microarchitectures - Intel"
codename | Gen9.5 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/gen9.5 + |
instance of | microarchitecture + |
manufacturer | Intel + |
microarchitecture type | GPU + |
name | Gen9.5 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |