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== Power delivery == | == Power delivery == | ||
− | Despite using the same socket ({{intel|FCLGA-1151}}) Coffee Lake | + | Despite using the same socket ({{intel|FCLGA-1151}}) Coffee Lake break compatibility with {{\\|Skylake (client)|Skylake}} and {{\\|Kaby Lake}} due to various enhancements to the power delivery of the processor in order to better handle the additional cores. |
− | In order to improve the power delivery of the chip and support | + | In order to improve the power delivery of the chip and support higher package-level current delivered for the additional cores, Intel needed to increase the number of pins that go to the power rails of the die. Since there is a practical limit as to how much current each pin is capable of delivering, a large number of additional pins that were previously unused/reserved have also been allocated for this purpose. The new hexa-core parts have 38 higher amperage rating. |
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Facts about "Coffee Lake - Microarchitectures - Intel"
codename | Coffee Lake + |
designer | Intel + |
first launched | October 5, 2017 + |
full page name | intel/microarchitectures/coffee lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + and dell + |
microarchitecture type | CPU + |
name | Coffee Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |