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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
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|introduction=October 5, 2017 | |introduction=October 5, 2017 | ||
|process=14 nm | |process=14 nm | ||
+ | |cores=2 | ||
+ | |cores 2=4 | ||
+ | |cores 3=6 | ||
+ | |cores 4=8 | ||
|type=Superscalar | |type=Superscalar | ||
|type 2=Superpipeline | |type 2=Superpipeline | ||
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|extension 7=SSE4.1 | |extension 7=SSE4.1 | ||
|extension 8=SSE4.2 | |extension 8=SSE4.2 | ||
+ | |extension 9=POPCNT | ||
|extension 10=AVX | |extension 10=AVX | ||
|extension 11=AVX2 | |extension 11=AVX2 | ||
|extension 12=AES | |extension 12=AES | ||
− | |extension 13= | + | |extension 13=PCLMUL |
+ | |extension 14=FSGSBASE | ||
+ | |extension 15=RDRND | ||
|extension 16=FMA3 | |extension 16=FMA3 | ||
+ | |extension 17=F16C | ||
+ | |extension 18=BMI | ||
+ | |extension 19=BMI2 | ||
+ | |extension 20=VT-x | ||
+ | |extension 21=VT-d | ||
+ | |extension 22=TXT | ||
+ | |extension 23=TSX | ||
+ | |extension 24=RDSEED | ||
+ | |extension 25=ADCX | ||
+ | |extension 26=PREFETCHW | ||
+ | |extension 27=CLFLUSHOPT | ||
+ | |extension 28=XSAVE | ||
+ | |extension 29=SGX | ||
+ | |extension 30=MPX | ||
|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=core | |l1i per=core | ||
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|predecessor=Kaby Lake | |predecessor=Kaby Lake | ||
|predecessor link=intel/microarchitectures/kaby lake | |predecessor link=intel/microarchitectures/kaby lake | ||
− | |successor | + | |successor=Ice Lake |
− | + | |successor link=intel/microarchitectures/ice lake (client) | |
− | |||
− | |successor | ||
|contemporary=Whiskey Lake | |contemporary=Whiskey Lake | ||
|contemporary link=intel/microarchitectures/whiskey_lake | |contemporary link=intel/microarchitectures/whiskey_lake | ||
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{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Core !! Abbrev | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
|- | |- | ||
− | | {{intel|Coffee Lake U|l=core}} || CFL-U | + | | {{intel|Coffee Lake U|l=core}} || CFL-U || Ultra-low power|| GT3e || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
|- | |- | ||
− | | {{intel|Coffee Lake H|l=core}} || CFL-H | + | | {{intel|Coffee Lake H|l=core}} || CFL-H || High-performance graphics || GT2 || Ultimate mobile performance, mobile workstations |
|- | |- | ||
− | | {{intel|Coffee Lake S|l=core}} || CFL-S | + | | {{intel|Coffee Lake S|l=core}} || CFL-S || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis |
|- | |- | ||
− | | {{intel|Coffee Lake R|l=core}} || CFL-R | + | | {{intel|Coffee Lake R|l=core}} || CFL-R || Mainstream performance (Refresh) || GT2 || Desktop performance to value, AiOs, and minis |
|- | |- | ||
− | | {{intel|Coffee Lake E|l=core}} || CFL-E | + | | {{intel|Coffee Lake E|l=core}} || CFL-E || Workstation || GT2 || Workstations and entry-level servers |
+ | |- | ||
+ | | {{intel|Coffee Lake X|l=core}} || CFL-X || Extreme Performance || || High performance desktops | ||
|} | |} | ||
== Brands == | == Brands == | ||
− | Intel released Coffee Lake under | + | Intel released Coffee Lake under 3 main brand families: |
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
|- | |- | ||
− | ! rowspan="2" | Logo !! rowspan="2" | Family | + | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features |
|- | |- | ||
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ||
|- | |- | ||
− | + | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || [[quad-core|Quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} | |
− | |||
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− | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} | ||
|- | |- | ||
− | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} | + | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} | + | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || Hexa || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} |
− | |||
− | |||
|} | |} | ||
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Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017. | Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017. | ||
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{{clear}} | {{clear}} | ||
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=== CPUID === | === CPUID === | ||
− | {| class="wikitable tc1 tc2 tc3 tc4 | + | {| class="wikitable tc1 tc2 tc3 tc4" |
− | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | + | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model |
− | |||
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|- | |- | ||
− | | rowspan="2" | | + | | rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x9 || 0xE |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model 158 |
|- | |- | ||
− | | rowspan="2" | | + | | rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x? || 0x? |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model ??? |
|} | |} | ||
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== Architecture == | == Architecture == | ||
[[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]] | [[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]] | ||
− | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50% | + | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50%, enabling much higher multi-threaded performance. The enhanced manufacturing process should allow Coffee Lake chips to be highly [[overclockable]]. |
=== Key changes from {{\\|Kaby Lake}}=== | === Key changes from {{\\|Kaby Lake}}=== | ||
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** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB) | ** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB) | ||
** Coffee Lake Refresh | ** Coffee Lake Refresh | ||
− | *** 100% more [[physical core|cores]] | + | *** 100% more [[physical core|cores]] 8, from 4) |
*** 100% larger [[last level cache]] (up to 16 MiB, from 8 MiB) | *** 100% larger [[last level cache]] (up to 16 MiB, from 8 MiB) | ||
+ | |||
+ | * Core | ||
+ | ** LSD has been re-enabled (Previously {{\\|skylake_(server)#Front-end|disabled}}) | ||
* Chipset | * Chipset | ||
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** {{intel|Core i5}} | ** {{intel|Core i5}} | ||
*** i5-7000 '''→''' i5-8000 | *** i5-7000 '''→''' i5-8000 | ||
− | *** | + | *** 2666 MT/s '''→''' 2666 MT/s |
*** [[quad-core]] '''→''' [[hexa-core]] | *** [[quad-core]] '''→''' [[hexa-core]] | ||
*** 6 MiB [[L3]] '''→''' 9 MiB [[L3]] | *** 6 MiB [[L3]] '''→''' 9 MiB [[L3]] | ||
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==== Entire SoC Overview (hexa) ==== | ==== Entire SoC Overview (hexa) ==== | ||
[[File:coffee lake soc block diagram.svg|900px]] | [[File:coffee lake soc block diagram.svg|900px]] | ||
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==== Individual Core ==== | ==== Individual Core ==== | ||
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**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
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=== Historical Trend === | === Historical Trend === | ||
− | Coffee Lake presents the largest change in the system architecture of Intel's mainstream | + | Coffee Lake presents the largest change in the system architecture of Intel's mainstream microarchitecutre since the introduction of {{\\|sandy_bridge_(client)#System_Architecture|Sandy Bridge}} in [[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=core}} core. Those initial quad-cores comprised of two separate dies interconnected in a [[multi-chip package]]. A coherent communication link was lacking and the aging [[front-side bus]] was used for as the die-to-die link. This configuration did not change through {{\\|Penryn}} up until the introduction of the Core i7 based on the {{\\|Nehalem}} microarchitecture in [[2008]]. Nehalem leveraged [[Moore's Law]] and Intel's [[45 nm process]] to incorporate all four cores onto a single die along with a large number of changes, particularly enhancing the uncore (now known as the System Agent). The Core i7-980X was also the first hexa-core consumer chip, although it was part of the enthusiast market segment and used a larger die. |
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− | ::[[File:sandy bridge-coffee lake overview change.svg| | + | ::[[File:sandy bridge-coffee lake overview change.svg|500px|left]] |
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− | + | [[File:quad to hexa mainstream die areas.svg|500px|right]] | |
+ | It can easily be seen how the natural evolution of [[Moore's Law]] and its affects on the die size of Intel's mainstream platform enables the addition of two more cores and their associated cache slices without sacrificing yield due to a bigger die. In fact, the hexa-core at 149 mm² is still considerably smaller than even the quad-core {{\\|Haswell}}-based chips. The pair of cores with their associated cache slices contributed an extra ~25mm². In fact, it can further be seen that even an 8-core Coffee Lake would be smaller than Haswell's quad-core at around 174 mm². It's worth noting that Coffee Lake is released concurrently with {{\\|Cannon Lake}} which is a [[10 nm]]-based microarchitecture for low-power mobile devices. Due to Intel's faithful [[die shrink]] of roughly x2.7 in density, an identical [[hexa-core]] Coffee Lake die on 10nm would result in a smaller die than any of the [[14 nm]] quad-core dies, possibly even the [[dual-core]] dies as well. | ||
{{clear}} | {{clear}} | ||
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==== Front-end ==== | ==== Front-end ==== | ||
− | + | Note that a bug associated with the Loop Stream Detector (LSD) has been fixed with Coffee Lake. See {{\\|skylake_(server)#Front-end|Skylake (server) § Front-end}}. | |
− | |||
==== Scheduler Ports & Execution Units ==== | ==== Scheduler Ports & Execution Units ==== | ||
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<tr><th>Port 2</th><td>Load, AGU</td></tr> | <tr><th>Port 2</th><td>Load, AGU</td></tr> | ||
<tr><th>Port 3</th><td>Load, AGU</td></tr> | <tr><th>Port 3</th><td>Load, AGU</td></tr> | ||
− | <tr><th>Port 4</th><td>Store</td></tr> | + | <tr><th>Port 4</th><td>Store, AGU</td></tr> |
<tr><th>Port 7</th><td>AGU</td></tr> | <tr><th>Port 7</th><td>AGU</td></tr> | ||
</table> | </table> | ||
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== Configurability == | == Configurability == | ||
− | Coffee Lake builds upon the Skylake platform, with the addition of the first hexa | + | Coffee Lake builds upon the Skylake platform, with the addition of the first hexa core die. Currently, the Coffee Lake family consists out of three dies, that are aimed towards the high performance market. |
<gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:left"> | <gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:left"> | ||
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| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | ||
|- | |- | ||
− | | {{intel|UHD Graphics 630}} || | + | | {{intel|UHD Graphics 630}} || 23/24 || GT2 || {{intel|Coffee Lake S|S|l=core}} || - || colspan="2" style="text-align: center;" | '''1.0''' || style="text-align: center;" | '''12''' || style="text-align: center;" | '''N/A''' || style="text-align: center;" | '''5.1''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" colspan="1" | '''2.1''' || style="text-align: center;" | '''2.0''' |
|} | |} | ||
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== Die == | == Die == | ||
− | Coffee Lake desktop and mobile come | + | Coffee Lake desktop and mobile come and 4 and 6 cores. Each variant has its own die. The major components of the die are: |
* System Agent | * System Agent | ||
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: [[File:coffee lake die (hexa core) (annotated).png|650px]] | : [[File:coffee lake die (hexa core) (annotated).png|650px]] | ||
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=== Additional Shots === | === Additional Shots === | ||
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<gallery mode=slideshow> | <gallery mode=slideshow> | ||
− | File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation | + | File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation core processor dies. |
− | |||
</gallery> | </gallery> | ||
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== Documents == | == Documents == | ||
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* [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]] | * [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]] | ||
* [[:File:8th-gen-intel-core-overview.pdf|8th generation Core product overview]] | * [[:File:8th-gen-intel-core-overview.pdf|8th generation Core product overview]] | ||
* [[:File:8th-gen-intel-core-product-brief.pdf|8th generation core product brief]] | * [[:File:8th-gen-intel-core-product-brief.pdf|8th generation core product brief]] | ||
* [[:File:8th-gen-intel-core-lineup-press-deck.pdf|8th generation core lineup]] | * [[:File:8th-gen-intel-core-lineup-press-deck.pdf|8th generation core lineup]] | ||
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== References == | == References == | ||
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | * Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | ||
* Intel 8th Generation Core announcement, Sept 25, 2017. | * Intel 8th Generation Core announcement, Sept 25, 2017. |
Facts about "Coffee Lake - Microarchitectures - Intel"
codename | Coffee Lake + |
designer | Intel + |
first launched | October 5, 2017 + |
full page name | intel/microarchitectures/coffee lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + and dell + |
microarchitecture type | CPU + |
name | Coffee Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |