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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
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|introduction=October 5, 2017 | |introduction=October 5, 2017 | ||
|process=14 nm | |process=14 nm | ||
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|l1i per=core | |l1i per=core | ||
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|core name 2=Coffee Lake H | |core name 2=Coffee Lake H | ||
|core name 3=Coffee Lake S | |core name 3=Coffee Lake S | ||
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|predecessor=Kaby Lake | |predecessor=Kaby Lake | ||
|predecessor link=intel/microarchitectures/kaby lake | |predecessor link=intel/microarchitectures/kaby lake | ||
− | |successor= | + | |successor=Icelake |
− | |successor link=intel/microarchitectures/ | + | |successor link=intel/microarchitectures/icelake |
− | + | |contemporary=Cannonlake | |
− | + | |contemporary link=intel/microarchitectures/cannonlake | |
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− | |contemporary | ||
− | |contemporary | ||
}} | }} | ||
− | '''Coffee Lake''' ('''CFL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of [[2017]] and is manufactured on Intel's mature [[14 nm process]]. Coffee Lake features the first series of mainstream [[hexa-core]] processors from Intel | + | '''Coffee Lake''' ('''CFL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of [[2017]] and is manufactured on Intel's mature [[14 nm process]]. Coffee Lake features the first series of mainstream [[hexa-core]] processors from Intel. |
== Codenames == | == Codenames == | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Core !! Abbrev | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
|- | |- | ||
− | | {{intel|Coffee Lake U|l=core}} || CFL-U | + | | {{intel|Coffee Lake U|l=core}} || CFL-U || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
|- | |- | ||
− | | {{intel|Coffee Lake H|l=core}} || CFL-H | + | | {{intel|Coffee Lake H|l=core}} || CFL-H || High-performance graphics || GT3e || Ultimate mobile performance, mobile workstations |
|- | |- | ||
− | | {{intel|Coffee Lake S|l=core}} || CFL-S | + | | {{intel|Coffee Lake S|l=core}} || CFL-S || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis |
|- | |- | ||
− | | {{intel|Coffee Lake | + | | {{intel|Coffee Lake X|l=core}} || CFL-X || Extreme Performance || || High performance desktops |
− | |||
− | |||
|} | |} | ||
== Brands == | == Brands == | ||
− | Intel released Coffee Lake under | + | Intel released Coffee Lake under 3 main brand families: |
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
|- | |- | ||
− | ! rowspan="2" | Logo !! rowspan="2" | Family | + | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features |
|- | |- | ||
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ||
|- | |- | ||
− | + | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || [[quad-core|Quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} | |
− | |||
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− | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} | ||
|- | |- | ||
− | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} | + | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} | + | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || Hexa || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} |
− | |||
− | |||
|} | |} | ||
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Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017. | Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017. | ||
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{{clear}} | {{clear}} | ||
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[[File:intel 14nm++.png|400px|right]] | [[File:intel 14nm++.png|400px|right]] | ||
{{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}} | {{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}} | ||
− | Coffee Lake is manufactured on [[Intel]]'s 3rd generation [[14 nm process]] called "14nm++". The process is the second enhanced version of the first which was used for the {{\\|Broadwell}} microarchitecture (first enhanced version was first used for {{\\|Kaby Lake}}). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides | + | Coffee Lake is manufactured on [[Intel]]'s 3rd generation [[14 nm process]] called "14nm++". The process is the second enhanced version of the first which was used for the {{\\|Broadwell}} microarchitecture (first enhanced version was first used for {{\\|Kaby Lake}}). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides 26% more performance for 52% less power. |
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=== CPUID === | === CPUID === | ||
− | {| class="wikitable tc1 tc2 tc3 tc4 | + | {| class="wikitable tc1 tc2 tc3 tc4" |
− | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | + | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model |
− | |||
− | |||
− | |||
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|- | |- | ||
− | | rowspan="2" | | + | | rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x9 || 0xE |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model 158 |
|- | |- | ||
− | | rowspan="2" | | + | | rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x? || 0x? |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model ??? |
|} | |} | ||
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− | |||
== Architecture == | == Architecture == | ||
[[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]] | [[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]] | ||
− | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50% | + | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50%, enabling much higher multi-threaded performance. The enhanced manufacturing process should allow Coffee Lake chips to be highly [[overclockable]]. |
=== Key changes from {{\\|Kaby Lake}}=== | === Key changes from {{\\|Kaby Lake}}=== | ||
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** 50% more [[physical core|cores]] (6, from 4) | ** 50% more [[physical core|cores]] (6, from 4) | ||
** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB) | ** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB) | ||
− | * | + | |
− | ** | + | * Core |
− | + | ** LSD has been re-enabled (Previously {{\\|skylake_(server)#Front-end|disabled}}) | |
* Chipset | * Chipset | ||
− | ** {{intel|Union Point|200 Series chipset|l=chipset}} → | + | ** {{intel|Union Point|200 Series chipset|l=chipset}} → 300 Series chipset (Cannonlake PCH)<!-- |
+ | *** Integrated Programmable (Open FW SDK) Quad-Core Audio DSP | ||
+ | *** Soundwire Digital Audio Interface | ||
*** Integrated USB 3.1 (10 Gib/s) | *** Integrated USB 3.1 (10 Gib/s) | ||
**** Up to 6 ports | **** Up to 6 ports | ||
− | *** Integrated | + | *** Integrated Intel wireless controller ([[IEEE 802.11ac]]) |
*** Integrated SDXC 3.0 controller | *** Integrated SDXC 3.0 controller | ||
+ | *** Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support | ||
+ | *** C10 & S0ix Support for Modern Standby--> | ||
* Memory | * Memory | ||
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** {{intel|Gen 9.5|l=arch}} GPUs (No Change) | ** {{intel|Gen 9.5|l=arch}} GPUs (No Change) | ||
** HD Graphics 6x0 '''→''' UHD Graphics 6x0 (Branding change only) | ** HD Graphics 6x0 '''→''' UHD Graphics 6x0 (Branding change only) | ||
− | |||
*** {{intel|HD Graphics 630}} '''→''' {{intel|UHD Graphics 630}} (No change) | *** {{intel|HD Graphics 630}} '''→''' {{intel|UHD Graphics 630}} (No change) | ||
* Families | * Families | ||
− | + | ** {{intel|Core i3}} gained 100% more [[physical core|cores]] (4, from 2) but dropped {{intel|hyper-threading}} support | |
− | + | ** {{intel|Core i5}} gained 50% more cores (6, from 4) | |
− | + | ** {{intel|Core i7}} gained 50% more cores (6, from 4) | |
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− | ** {{intel|Core i3}} | ||
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− | ** {{intel|Core i5}} | ||
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− | ** {{intel|Core i7}} | ||
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=== Block Diagram === | === Block Diagram === | ||
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==== Entire SoC Overview (hexa) ==== | ==== Entire SoC Overview (hexa) ==== | ||
[[File:coffee lake soc block diagram.svg|900px]] | [[File:coffee lake soc block diagram.svg|900px]] | ||
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==== Individual Core ==== | ==== Individual Core ==== | ||
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**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
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=== Historical Trend === | === Historical Trend === | ||
− | Coffee Lake presents the largest change in the system architecture of Intel's mainstream | + | Coffee Lake presents the largest change in the system architecture of Intel's mainstream microarchitecutre since the introduction of {{\\|sandy_bridge_(client)#System_Architecture|Sandy Bridge}} in [[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=core}} core. Those initial quad-cores comprised of two separate dies interconnected in a [[multi-chip package]]. A coherent communication link was lacking and the aging [[front-side bus]] was used for as the die-to-die link. This configuration did not change through {{\\|Penryn}} up until the introduction of the Core i7 Extreme based on the {{\\|Nehalem}} microarchitecture in [[2008]]. Nehalem leveraged [[Moore's Law]] and Intel's [[45 nm process]] to incorporate all four cores onto a single die along with a large number of changes, particularly enhancing the uncore (now known as the System Agent). |
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With the introduction of {{\\|Sandy Bridge}} in 2011, the entire system architecture was reworked. A particular goal of Sandy Bridge was {{\\|Sandy Bridge#Configurability|its configurability}}. Intel wanted to be able to use a single design across multiple market segments without having to spend extra resources on multiple physical designs. A large part of its modularity came from the {{\\|sandy_bridge_(client)#Ring_Interconnect|ring interconnect Sandy Bridge implemented}}. It's worth pointing out that the ring implementation in Sandy Bridge is an enhanced version largely based on an implementation first incorporated into the Nehalem-EX server parts. The ring allowed Intel to integrate the {{intel|System Agent}} and the [[integrated graphics]] on-die in Sandy Bridge. | With the introduction of {{\\|Sandy Bridge}} in 2011, the entire system architecture was reworked. A particular goal of Sandy Bridge was {{\\|Sandy Bridge#Configurability|its configurability}}. Intel wanted to be able to use a single design across multiple market segments without having to spend extra resources on multiple physical designs. A large part of its modularity came from the {{\\|sandy_bridge_(client)#Ring_Interconnect|ring interconnect Sandy Bridge implemented}}. It's worth pointing out that the ring implementation in Sandy Bridge is an enhanced version largely based on an implementation first incorporated into the Nehalem-EX server parts. The ring allowed Intel to integrate the {{intel|System Agent}} and the [[integrated graphics]] on-die in Sandy Bridge. | ||
[[File:sandy bridge ring scalability.svg|right|100px]] | [[File:sandy bridge ring scalability.svg|right|100px]] | ||
− | Each of those components had its own ring agent (in addition to the individual core), allowing for efficient transfer of data between the GPU, the SA, and the individual cores and caches. The final result was a complete system on a chip | + | Each of those components had its own ring agent (in addition to the individual core), allowing for efficient transfer of data between the GPU, the SA, and the individual cores and caches. The final result was a complete system on a chip with four cores and a 12 EU GPU on a single die measuring consisting of 1.16 billion transistors on a 216 mm² die. |
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− | ::[[File:sandy bridge-coffee lake overview change.svg| | + | ::[[File:sandy bridge-coffee lake overview change.svg|500px|left]] |
− | [[File:quad to hexa mainstream die areas.svg| | + | [[File:quad to hexa mainstream die areas.svg|500px|right]] |
− | + | It can easily be seen how the natural evolution of [[Moore's Law]] and its affects on the die size of Intel's mainstream platform enables the addition of two more cores and their associated cache slices without sacrificing yield due to a bigger die. In fact, the hexa-core at 149 mm² is still considerably smaller than even the quad-core {{\\|Haswell}}-based chips. The pair of cores with their associated cache slices contributed an extra ~25mm². In fact, it can further be seen that even an 8-core Coffee Lake would be smaller than Haswell's quad-core at around 174 mm². It's worth noting that Coffee Lake is released concurrently with {{\\|Cannonlake}} which is a [[10 nm]]-based microarchitecture for low-power mobile devices. Due to Intel's faithful [[die shrink]] of roughly x2.7 in density, an identical [[hexa-core]] Coffee Lake die on 10nm would result in a smaller die than any of the [[14 nm]] quad-core dies, possibly even the [[dual-core]] dies as well. | |
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− | In | ||
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{{clear}} | {{clear}} | ||
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==== Front-end ==== | ==== Front-end ==== | ||
− | + | Note that a bug associated with the Loop Stream Detector (LSD) has been fixed with Coffee Lake. See {{\\|skylake_(server)#Front-end|Skylake (server) § Front-end}}. | |
− | |||
==== Scheduler Ports & Execution Units ==== | ==== Scheduler Ports & Execution Units ==== | ||
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<tr><th>Port 2</th><td>Load, AGU</td></tr> | <tr><th>Port 2</th><td>Load, AGU</td></tr> | ||
<tr><th>Port 3</th><td>Load, AGU</td></tr> | <tr><th>Port 3</th><td>Load, AGU</td></tr> | ||
− | <tr><th>Port 4</th><td>Store</td></tr> | + | <tr><th>Port 4</th><td>Store, AGU</td></tr> |
<tr><th>Port 7</th><td>AGU</td></tr> | <tr><th>Port 7</th><td>AGU</td></tr> | ||
</table> | </table> | ||
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== Configurability == | == Configurability == | ||
− | Coffee Lake builds upon the Skylake platform, with the addition of the first hexa | + | Coffee Lake builds upon the Skylake platform, with the addition of the first hexa core die. Currently the Coffee Lake family consists out of two dies, aimed towards the high performance market. |
<gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:left"> | <gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:left"> | ||
− | |||
File:4 core hp gt2 skylake.svg|Quad-core die, GT2 GPU, High Power | File:4 core hp gt2 skylake.svg|Quad-core die, GT2 GPU, High Power | ||
File:6 core hp gt2 coffeelake.svg|Hexa-core die, GT2 GPU, High Power | File:6 core hp gt2 coffeelake.svg|Hexa-core die, GT2 GPU, High Power | ||
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== Graphics == | == Graphics == | ||
{{main|intel/microarchitectures/gen9.5|l1=Gen9.5}} | {{main|intel/microarchitectures/gen9.5|l1=Gen9.5}} | ||
− | Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide | + | Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, and [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Coffee Lake's graphics are identical to Kaby Lake and have native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit). |
{| class="wikitable tc2 tc3" | {| class="wikitable tc2 tc3" | ||
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| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | ||
|- | |- | ||
− | | {{intel|UHD Graphics 630}} || | + | | {{intel|UHD Graphics 630}} || 23/24 || GT2 || {{intel|Coffee Lake S|S|l=core}} || - || colspan="2" style="text-align: center;" | '''1.0''' || style="text-align: center;" | '''12''' || style="text-align: center;" | '''N/A''' || style="text-align: center;" | '''5.1''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" colspan="1" | '''2.1''' || style="text-align: center;" | '''2.0''' |
|} | |} | ||
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== Power delivery == | == Power delivery == | ||
− | Despite using the same socket ({{intel|FCLGA-1151}}) Coffee Lake | + | Despite using the same socket ({{intel|FCLGA-1151}}) Coffee Lake break compatibility with {{\\|Skylake (client)|Skylake}} and {{\\|Kaby Lake}} due to various enhancements to the power delivery of the processor in order to better handle the additional cores. |
− | In order to improve the power delivery of the chip and support | + | In order to improve the power delivery of the chip and support higher package-level current delivered for the additional cores, Intel needed to increase the number of pins that go to the power rails of the die. Since there is a practical limit as to how much current each pin is capable of delivering, a large number of additional pins that were previously unused/reserved have also been allocated for this purpose. The new hexa-core parts have 38 higher amperage rating. |
{| class="wikitable" | {| class="wikitable" | ||
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! || Skylake/Kaby Lake || Coffee Lake | ! || Skylake/Kaby Lake || Coffee Lake | ||
|- | |- | ||
− | ! Socket || FCLGA-1151 | + | ! Socket || FCLGA-1151 || FCLGA-1151 |
|- | |- | ||
| Contacts || 1151 || 1151 | | Contacts || 1151 || 1151 | ||
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== Die == | == Die == | ||
− | Coffee Lake desktop and mobile come | + | Coffee Lake desktop and mobile come and 4 and 6 cores. Each variant has its own die. The major components of the die are: |
* System Agent | * System Agent | ||
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* 11 metal layers | * 11 metal layers | ||
* 126 mm² die size | * 126 mm² die size | ||
− | * 4 CPU cores + | + | * 4 CPU cores + 23 GPU EUs |
=== Hexa-Core === | === Hexa-Core === | ||
* [[14 nm process|14 nm++ process]] | * [[14 nm process|14 nm++ process]] | ||
* 11 metal layers | * 11 metal layers | ||
− | * | + | * 149 mm² die size |
− | |||
* 6 CPU cores + 24 GPU EUs | * 6 CPU cores + 24 GPU EUs | ||
− | : [[File:coffee lake die (hexa core).png | + | : [[File:coffee lake die (hexa core).png|650px]] |
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− | : [[File:coffee lake die ( | + | : [[File:coffee lake die (quad core) (annotated).png|650px]] |
=== Additional Shots === | === Additional Shots === | ||
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<gallery mode=slideshow> | <gallery mode=slideshow> | ||
− | File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation | + | File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation core processor dies. |
− | |||
</gallery> | </gallery> | ||
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|userparam=23:22 | |userparam=23:22 | ||
|mainlabel=- | |mainlabel=- | ||
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}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Coffee Lake]]}} | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Coffee Lake]]}} | ||
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== Documents == | == Documents == | ||
− | |||
* [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]] | * [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]] | ||
* [[:File:8th-gen-intel-core-overview.pdf|8th generation Core product overview]] | * [[:File:8th-gen-intel-core-overview.pdf|8th generation Core product overview]] | ||
* [[:File:8th-gen-intel-core-product-brief.pdf|8th generation core product brief]] | * [[:File:8th-gen-intel-core-product-brief.pdf|8th generation core product brief]] | ||
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== References == | == References == | ||
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | * Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | ||
* Intel 8th Generation Core announcement, Sept 25, 2017. | * Intel 8th Generation Core announcement, Sept 25, 2017. |
Facts about "Coffee Lake - Microarchitectures - Intel"
codename | Coffee Lake + |
designer | Intel + |
first launched | October 5, 2017 + |
full page name | intel/microarchitectures/coffee lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + and dell + |
microarchitecture type | CPU + |
name | Coffee Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |