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|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
|manufacturer 2=dell
 
 
|introduction=October 5, 2017
 
|introduction=October 5, 2017
 
|process=14 nm
 
|process=14 nm
|type=Superscalar
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|cores=4
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|core name 2=Coffee Lake H
 
|core name 2=Coffee Lake H
 
|core name 3=Coffee Lake S
 
|core name 3=Coffee Lake S
|core name 4=Coffee Lake R
 
|core name 5=Coffee Lake E
 
 
|predecessor=Kaby Lake
 
|predecessor=Kaby Lake
 
|predecessor link=intel/microarchitectures/kaby lake
 
|predecessor link=intel/microarchitectures/kaby lake
|successor=Comet Lake
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|successor=Cannonlake
|successor link=intel/microarchitectures/comet lake
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|successor link=intel/microarchitectures/cannonlake
|successor 2=Ice Lake
 
|successor 2 link=intel/microarchitectures/ice lake (client)
 
|contemporary=Whiskey Lake
 
|contemporary link=intel/microarchitectures/whiskey_lake
 
|contemporary 2=Cannon Lake
 
|contemporary 2 link=intel/microarchitectures/cannon_lake
 
 
}}
 
}}
'''Coffee Lake''' ('''CFL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of [[2017]] and is manufactured on Intel's mature [[14 nm process]]. Coffee Lake features the first series of mainstream [[hexa-core]] processors from Intel. In [[2018]], Intel refreshed the Coffee Lake lineup to incorporate their first series of mainstream [[octa-core]] processors.
+
'''Coffee Lake''' ('''CFL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of [[2017]] and is manufactured on Intel's mature [[14 nm process]]. Coffee Lake features the first series of mainstream [[hexa-core]] processors from Intel.
  
 
== Codenames ==
 
== Codenames ==
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
! Core !! Abbrev !! Platform !! Description !! Graphics !! Target
+
! Core !! Abbrev !! Description !! Graphics !! Target
 
|-
 
|-
| {{intel|Coffee Lake U|l=core}} || CFL-U || || Ultra-low power|| GT3e || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
+
| {{intel|Coffee Lake U|l=core}} || CFL-U || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
|-
 
|-
| {{intel|Coffee Lake H|l=core}} || CFL-H || || High-performance graphics || GT2 || Ultimate mobile performance, mobile workstations
+
| {{intel|Coffee Lake H|l=core}} || CFL-H || High-performance graphics || GT3e || Ultimate mobile performance, mobile workstations
 
|-
 
|-
| {{intel|Coffee Lake S|l=core}} || CFL-S || || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis
+
| {{intel|Coffee Lake S|l=core}} || CFL-S || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis
 
|-
 
|-
| {{intel|Coffee Lake R|l=core}} || CFL-R || || Mainstream performance (Refresh) || GT2 || Desktop performance to value, AiOs, and minis
+
| {{intel|Coffee Lake X|l=core}} || CFL-X || Extreme Performance || || High performance desktops
|-
 
| {{intel|Coffee Lake E|l=core}} || CFL-E || Mehlow || Workstation || GT2 || Workstations and entry-level servers
 
 
|}
 
|}
  
 
== Brands ==
 
== Brands ==
Intel released Coffee Lake under 6 main brand families:
+
Intel released Coffee Lake under 3 main brand families:
  
 
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
 
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
 
|-
 
|-
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | Generation !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
+
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
 
|-
 
|-
 
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
 
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
 
|-
 
|-
| [[File:intel celeron (2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || 4xxx || Entry-level Budget || [[dual-core|Dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}}
+
| [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || [[quad-core|Quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
 
|-
 
|-
| [[File:intel pentium (2015).png|50px|link=intel/pentium]] || {{intel|Pentium Gold}} || 5xxx || Budget || [[dual-core|Dual]] || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}}
+
| [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
|-
 
|-
| [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || 8th/9th Gen || Low-end Performance || [[quad-core|Quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}}
+
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || Hexa || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
 
| [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || 8th/9th Gen || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
|-
 
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || 8th/9th Gen || High-end Performance || Hexa || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
|-
 
| [[File:core i9 logo (2015).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || 9th Gen || Ultra Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
 
|}
 
|}
  
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Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017.
 
Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017.
 
In October 2018, Intel introduced a refresh of Coffee Lake, adding more cores and increasing their clock frequencies.
 
  
 
{{clear}}
 
{{clear}}
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[[File:intel 14nm++.png|400px|right]]
 
[[File:intel 14nm++.png|400px|right]]
 
{{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}}
 
{{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}}
Coffee Lake is manufactured on [[Intel]]'s 3rd generation [[14 nm process]] called "14nm++". The process is the second enhanced version of the first which was used for the {{\\|Broadwell}} microarchitecture (first enhanced version was first used for {{\\|Kaby Lake}}). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides up to 26% more performance at the same power or 52% less power at the same performance.
+
Coffee Lake is manufactured on [[Intel]]'s 3rd generation [[14 nm process]] called "14nm++". The process is the second enhanced version of the first which was used for the {{\\|Broadwell}} microarchitecture (first enhanced version was first used for {{\\|Kaby Lake}}). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides 26% more performance for 52% less power.
  
  
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Note that while both "14nm" and "14nm+" used the same transistor geometry, the "14nm++" actually uses a more relaxed contacted poly pitch of 84 nm (from previously 70nm). There is no real density change despite this change likely due to various design techniques such as reduced fins where unnecessary.
+
Note that while both "14nm" and "14nm+" used the same transistor geometry, the "14nm++" actually uses a more relaxed contacted poly pitch of 84 nm (from previously 70nm). It's unknown what kind of effect this has on the overall density, if any.
 
 
{| class="wikitable"
 
|-
 
! !! Kaby Lake !! Coffee Lake !! Δ
 
|-
 
| || [[14 nm]] || 14 nm ||
 
|-
 
| Gate Pitch || 70 nm || 84 nm || 1.20x
 
|-
 
| Interconnect Pitch || 52 nm || 52 nm || 1.00x
 
|}
 
  
 
{{clear}}
 
{{clear}}
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=== CPUID ===
 
=== CPUID ===
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
+
{| class="wikitable tc1 tc2 tc3 tc4"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
+
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
|-
 
| rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 6 || 0x6 || 0x8 || 0xE || 0xA
 
|-
 
| colspan="5" | Family 6 Model 142 Stepping 10
 
|-
 
| rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x9 || 0xE || 0xA
 
|-
 
| colspan="5" | Family 6 Model 158 Stepping 10
 
 
|-
 
|-
| rowspan="2" | i3-9350KF || 0 || 0x6 || 0x9 || 0xE || 0xB
+
| rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x? || 0xE?
 
|-
 
|-
| colspan="5" | Family 6 Model 158 Stepping 11
+
| colspan="4" | Family 6 Model ???
 
|-
 
|-
| rowspan="2" | 94xx-99xx || 0 || 0x6 || 0x9 || 0xE || 0xC,0xD
+
| rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x? || 0x?
 
|-
 
|-
| colspan="5" | Family 6 Model 158 Stepping 12,13
+
| colspan="4" | Family 6 Model ???
 
|}
 
|}
 
Meltdown and L1TF are fixed in hardware starting with stepping 12. Stepping 13 adds mitigation against Speculative Store Bypass.
 
  
 
== Architecture ==
 
== Architecture ==
 
[[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]]
 
[[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]]
While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50% (later by 100%), enabling much higher multi-threaded performance. The enhanced manufacturing process should allow Coffee Lake chips to be highly [[overclockable]].
+
While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50%, enabling much higher multi-threaded performance. The enhanced manufacturing process should allowed Coffee Lake chips to be highly [[overclockable]].
  
 
=== Key changes from {{\\|Kaby Lake}}===
 
=== Key changes from {{\\|Kaby Lake}}===
 
* Enhanced "14nm++" process results in higher turbo frequencies
 
* Enhanced "14nm++" process results in higher turbo frequencies
* IPC improvement from larger cache for various workloads, but actual core is unchanged
+
* IPC improvement from larger cache, but actual core is unchanged
  
 
* System Architecture
 
* System Architecture
 
** 50% more [[physical core|cores]] (6, from 4)
 
** 50% more [[physical core|cores]] (6, from 4)
 
** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB)
 
** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB)
** Coffee Lake Refresh
 
*** 100% more [[physical core|cores]] (8, from 4)
 
*** 100% larger [[last level cache]] (up to 16 MiB, from 8 MiB)
 
  
 
* Chipset
 
* Chipset
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
+
** {{intel|Union Point|200 Series chipset|l=chipset}} → 300 Series chipset (Cannonlake PCH)<!--
 +
*** Integrated Programmable (Open FW SDK) Quad-Core Audio DSP
 +
*** Soundwire Digital Audio Interface
 
*** Integrated USB 3.1 (10 Gib/s)
 
*** Integrated USB 3.1 (10 Gib/s)
 
**** Up to 6 ports
 
**** Up to 6 ports
*** Integrated {{intel|CNVi|Intel wireless controller}} ([[IEEE 802.11ac]])
+
*** Integrated Intel wireless controller ([[IEEE 802.11ac]])
 
*** Integrated SDXC 3.0 controller
 
*** Integrated SDXC 3.0 controller
 +
*** Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support
 +
*** C10 & S0ix Support for Modern Standby-->
  
 
* Memory
 
* Memory
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** {{intel|Gen 9.5|l=arch}} GPUs (No Change)
 
** {{intel|Gen 9.5|l=arch}} GPUs (No Change)
 
** HD Graphics 6x0 '''→''' UHD Graphics 6x0 (Branding change only)
 
** HD Graphics 6x0 '''→''' UHD Graphics 6x0 (Branding change only)
*** {{intel|HD Graphics 610}} '''→''' {{intel|UHD Graphics 610}} (No change)
 
 
*** {{intel|HD Graphics 630}} '''→''' {{intel|UHD Graphics 630}} (No change)
 
*** {{intel|HD Graphics 630}} '''→''' {{intel|UHD Graphics 630}} (No change)
  
 
* Families
 
* Families
** {{intel|Celeron}}
+
** {{intel|Core i3}} gained 100% more [[physical core|cores]] (4, from 2) but dropped {{intel|hyper-threading}} support
*** G3900 '''→''' G4900
+
** {{intel|Core i5}} gained 50% more cores (6, from 4)
*** 2133 MT/s '''→''' 2400 MT/s
+
** {{intel|Core i7}} gained 50% more cores (6, from 4)
*** Features removed: {{intel|MPX}}, {{intel|OS Guard}}
 
** {{intel|Pentium Gold}}
 
*** G4500 '''→''' G5500
 
*** 2133 MT/s '''→''' 2400 MT/s
 
*** 3 MiB [[L3]] '''→''' 4 MiB [[L3]]
 
*** Features removed: {{intel|MPX}}, {{intel|OS Guard}}
 
** {{intel|Core i3}}
 
*** i3-7000 '''→''' i3-8000
 
*** [[dual-core]] '''→''' [[quad-core]]
 
*** 3/4 MiB [[L3]] '''→''' 6/8 MiB [[L3]]
 
*** Features removed: {{intel|hyper-threading}}
 
** {{intel|Core i5}}
 
*** i5-7000 '''→''' i5-8000
 
*** 2400 MT/s '''→''' 2666 MT/s
 
*** [[quad-core]] '''→''' [[hexa-core]]
 
*** 6 MiB [[L3]] '''→''' 9 MiB [[L3]]
 
** {{intel|Core i7}}
 
*** i7-7000 '''→''' i7-8000
 
*** 2400 MT/s '''→''' 2666 MT/s
 
*** [[quad-core]] '''→''' [[hexa-core]]
 
*** 8 MiB [[L3]] '''→''' 12 MiB [[L3]]
 
  
 
=== Block Diagram ===
 
=== Block Diagram ===
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==== Entire SoC Overview (hexa) ====
 
==== Entire SoC Overview (hexa) ====
 
[[File:coffee lake soc block diagram.svg|900px]]
 
[[File:coffee lake soc block diagram.svg|900px]]
 
==== Entire SoC Overview (octa) ====
 
[[File:coffee lake r soc block diagram.svg|1000px]]
 
  
 
==== Individual Core ====
 
==== Individual Core ====
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**** fixed partition
 
**** fixed partition
 
*** 1G page translations:
 
*** 1G page translations:
**** 4 entries; 4-way set associative
+
**** 4 entries; fully associative
 
**** fixed partition
 
**** fixed partition
 
** STLB
 
** STLB
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**** fixed partition
 
**** fixed partition
 
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
 
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
 
 
* '''Note:''' STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Coffee Lake erratum CFL084 recommends software to simply ignore that value.
 
  
 
== Overview ==
 
== Overview ==
 
[[File:coffee lake overview.svg|right|500px]]
 
[[File:coffee lake overview.svg|right|500px]]
The Coffee Lake system on a chip consists of a five major components: CPU [[physical core|cores]], [[last level cache|LLC]], Ring interconnect, {{intel|System Agent}}, and the [[integrated graphics]]. The core architecture in Coffee Lake, like in {{\\|Kaby Lake}}, as not changed from {{\\|Skylake}}. This is also true for the integrated graphics which is identical to the one incorporated in {{\\|Kaby Lake}} and from a platform point of view, the I/O has not changed (supporting up to 3 displays and providing 16 PCIe Gen 3 lanes). Coffee Lake, however, has brought a relatively large change to the overall system architecture by introducing two additional [[physical cores]] into its mainstream processor die. Those two cores also come with up to 2 MiB of LLC slice per core (for up to 4 MiB of additional [[last level cache]]).
+
The Coffee Lake system on a chip consists of a five major components: CPU [[physical core|cores]], [[LLC]], Ring interconnect, {{intel|System Agent}}, and the [[integrated graphics]]. The core architecture in Coffee Lake, like in {{\\|Kaby Lake}}, as not changed from {{\\|Skylake}}. This is also true for the integrated graphics which is identical to the one incorporated in {{\\|Kaby Lake}} and from a platform point of view, the I/O has not changed (supporting up to 3 displays and providing 16 PCIe Gen 3 lanes). Coffee Lake, however, has brought a relatively large change to the overall system architecture by introducing two additional [[physical cores]] into its mainstream processor die. Those two cores also come with up to 2 MiB of LLC slice per core (for up to 4 MiB of additional [[last level cache]]).
  
 
In addition to improving multi-thread performance considerably by introducing 50% or two more cores as well as up to four additional threads, the added addition of up to 4 MiB of cache should have a positive impact on most single-thread performance.
 
In addition to improving multi-thread performance considerably by introducing 50% or two more cores as well as up to four additional threads, the added addition of up to 4 MiB of cache should have a positive impact on most single-thread performance.
  
 
=== Historical Trend ===
 
=== Historical Trend ===
Coffee Lake presents the largest change in the system architecture of Intel's mainstream microarchitecture since the introduction of {{\\|sandy_bridge_(client)#System_Architecture|Sandy Bridge}} in [[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=core}} core. Those initial quad-cores comprised of two separate dies interconnected in a [[multi-chip package]]. A coherent communication link was lacking and the aging [[front-side bus]] was used for as the die-to-die link. This configuration did not change through {{\\|Penryn}} up until the introduction of the Core i7 based on the {{\\|Nehalem}} microarchitecture in [[2008]]. Nehalem leveraged [[Moore's Law]] and Intel's [[45 nm process]] to incorporate all four cores onto a single die along with a large number of changes, particularly enhancing the uncore (now known as the System Agent). The Core i7-980X was also the first hexa-core consumer chip, although it was part of the enthusiast market segment and used a larger die.
+
Coffee Lake presents the largest change in the system architecture of Intel's mainstream microarchitecutre since the introduction of {{\\|sandy_bridge_(client)#System_Architecture|Sandy Bridge}} in [[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=core}} core. Those initial quad-cores comprised of two separate dies interconnected in a [[multi-chip package]]. This configuration did not change through {{\\|Penryn}} up until the introduction of the Core i7 Extreme based on the {{\\|Nehalem}} microarchitecture in [[2008]]. Nehalem leveraged [[Moore's Law]] and Intel's [[45 nm process]] to incorporate all four cores onto a single die along with a large number of changes, particularly enhancing the uncore (now known as the System Agent).
 
 
 
 
::[[File:penryn-nehalem overview change.svg|500px|left]]
 
 
 
 
 
With the introduction of {{\\|Sandy Bridge}} in 2011, the entire system architecture was reworked. A particular goal of Sandy Bridge was {{\\|Sandy Bridge#Configurability|its configurability}}. Intel wanted to be able to use a single design across multiple market segments without having to spend extra resources on multiple physical designs. A large part of its modularity came from the {{\\|sandy_bridge_(client)#Ring_Interconnect|ring interconnect Sandy Bridge implemented}}. It's worth pointing out that the ring implementation in Sandy Bridge is an enhanced version largely based on an implementation first incorporated into the Nehalem-EX server parts. The ring allowed Intel to integrate the {{intel|System Agent}} and the [[integrated graphics]] on-die in Sandy Bridge.
 
[[File:sandy bridge ring scalability.svg|right|100px]]
 
Each of those components had its own ring agent (in addition to the individual core), allowing for efficient transfer of data between the GPU, the SA, and the individual cores and caches. The final result was a complete system on a chip (SoC) with four cores and a 12 EU GPU on a single die measuring consisting of 1.16 billion transistors on a 216 mm² die.
 
 
 
 
 
::[[File:nehalem-sandy bridge overview change.svg|500px|right]]
 
  
 +
[[File:sandy bridge ring scalability.svg|left|150px]]
 +
With the introduction of {{\\|Sandy Bridge}} in 2011, the entire system architecture was reworked. A particular goal of Sandy Bridge was {{\\|Sandy Bridge#Configurability|its configurability}}. Intel wanted to be able to use a single design across multiple market segments without having to spend extra resources on multiple physical designs. A large part of its modularity came from the {{\\|sandy_bridge_(client)#Ring_Interconnect|ring interconnect Sandy Bridge implemented}}. It's worth pointing out that the implementation in Sandy Bridge is largely based on an enhanced version first implemented in Nehalem-EX server parts. The ring allowed Intel to integrate the {{intel|System Agent}} and the [[integrated graphics]] on-die in Sandy Bridge. Each of those components had its own ring agent (in addition to the individual core), allowing for efficient transfer of data between the GPU, the SA, and the individual cores and caches. The final result was a complete system on a chip with four cores and a 12 EU GPU on a single die measuring consisting of 1.16 billion transistors on a 216 mm² die.
  
 
From {{\\|Sandy Bridge}} through [[22 nm]] {{\\|Haswell}} and through [[14 nm]] {{\\|Skylake}}, the [[die shrink|die shrunk]] considerably, even after {{\\|skylake_(client)#Key_changes_from_Broadwell|large amount of enhancements}} (and thus transistors) were done to the microarchitecture. With the aid of [[Moore's Law]], the [[quad-core]] die in Coffee Lake's predecessor, {{\\|Kaby Lake}}, has reached 126 mm² - 42% smaller than the quad-core Sandy Bridge while packing over 3 times as much transistors.
 
From {{\\|Sandy Bridge}} through [[22 nm]] {{\\|Haswell}} and through [[14 nm]] {{\\|Skylake}}, the [[die shrink|die shrunk]] considerably, even after {{\\|skylake_(client)#Key_changes_from_Broadwell|large amount of enhancements}} (and thus transistors) were done to the microarchitecture. With the aid of [[Moore's Law]], the [[quad-core]] die in Coffee Lake's predecessor, {{\\|Kaby Lake}}, has reached 126 mm² - 42% smaller than the quad-core Sandy Bridge while packing over 3 times as much transistors.
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Since Coffee Lake utilizes Intel's 3rd generation enhanced [[14 nm process|14nm++ process]] which has reached maturity and healthy yield, Intel can afford to increase the amount of cores by 50% from [[4 cores|4]] to [[6 cores]]. This is also possible thanks to the existing ring interconnect that was designed specifically to be able to support this configuration. In addition to the two added cores, there are two addition LLC slices - each consisting of 2 MiB in size.
 
Since Coffee Lake utilizes Intel's 3rd generation enhanced [[14 nm process|14nm++ process]] which has reached maturity and healthy yield, Intel can afford to increase the amount of cores by 50% from [[4 cores|4]] to [[6 cores]]. This is also possible thanks to the existing ring interconnect that was designed specifically to be able to support this configuration. In addition to the two added cores, there are two addition LLC slices - each consisting of 2 MiB in size.
  
 +
<div style="display: block; margin: 0 auto; text-align: center;">[[File:core to coffee die evolution.svg|650px]]</div>
  
::[[File:sandy bridge-coffee lake overview change.svg|600px]]
 
  
 
+
[[File:quad to hexa mainstream die areas.svg|500px|right]]
[[File:quad to hexa mainstream die areas.svg|thumb|right|die size over time]]
+
It can easily be seen how the natural evolution of [[Moore's Law]] and its affects on the die size of Intel's mainstream platform enables the addition of two more cores and their associated cache slices without sacrificing yield due to a bigger die. In fact, the hexa-core at 149 mm² is still considerably smaller than even the quad-core {{\\|Haswell}}-based chips. The pair of cores with their associated cache slices contributed an extra ~25mm². It's worth noting that Coffee Lake is released concurrently with {{\\|Cannonlake}} which is a [[10 nm]]-based microarchitecture for low-power mobile devices. Due to Intel's faithful [[die shrink]] of roughly x2.7 in density, a [[hexa-core]] Kaby Lake would result in a smaller die than any of the [[14 nm]] quad-core dies, possibly even the [[dual-core]] dies as well.
 
 
 
 
Intel's rather faithful [[process shrink]] which has resulted in over 2.4x cell-level density improvement had a significant impact on the die size of their mainstream platform which enabled the addition of two more cores and their associated cache slices without sacrificing yield due to a bigger die. In fact, the hexa-core at 149 mm² is still considerably smaller than even the quad-core {{\\|Haswell}}-based chips. The pair of cores with their associated cache slices and the {{intel|ring interconnect}} agent contributed an extra ~25mm².
 
 
 
 
 
:[[File:coffee lake ring explanation 1.svg|600px]]
 
 
 
:[[File:coffee lake ring addition.png|600px]]
 
 
 
 
 
In late 2018 Intel introduced a refresh of Coffee Lake which further bumped the core count to eight. The 8-core refresh still yielded a smaller die than Haswell's quad-core, at around 174 mm².  It's worth noting that Coffee Lake is released concurrently with {{\\|Cannon Lake}} which is a [[10 nm]]-based microarchitecture for low-power mobile devices. Due to Intel's faithful [[die shrink]] of roughly x2.7 in density, an identical [[hexa-core]] Coffee Lake die on 10nm would result in a smaller die than any of the [[14 nm]] quad-core dies, possibly even the [[dual-core]] dies as well.
 
 
 
::[[File:coffee lake-coffee lake refresh overview change.svg|600px]]
 
  
 
{{clear}}
 
{{clear}}
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{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}}
 
{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}}
 
Coffee Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}.
 
Coffee Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}.
 
==== Front-end ====
 
 
The LSD remains disabled in Coffee Lake, see {{\\|skylake_(server)#Front-end|Skylake (server) § Front-end}}.
 
  
 
==== Scheduler Ports & Execution Units ====
 
==== Scheduler Ports & Execution Units ====
Line 405: Line 331:
 
<tr><th>Port 2</th><td>Load, AGU</td></tr>
 
<tr><th>Port 2</th><td>Load, AGU</td></tr>
 
<tr><th>Port 3</th><td>Load, AGU</td></tr>
 
<tr><th>Port 3</th><td>Load, AGU</td></tr>
<tr><th>Port 4</th><td>Store</td></tr>
+
<tr><th>Port 4</th><td>Store, AGU</td></tr>
 
<tr><th>Port 7</th><td>AGU</td></tr>
 
<tr><th>Port 7</th><td>AGU</td></tr>
 
</table>
 
</table>
Line 441: Line 367:
 
|colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included.
 
|colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included.
 
|}
 
|}
 
== Configurability ==
 
Coffee Lake builds upon the Skylake platform, with the addition of the first hexa core die followed by the first octa-core die. Currently, the Coffee Lake family consists of four dies, aimed towards the high-performance market.
 
 
<gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:left">
 
File:dual core hp gt2 skylake.svg|Dual-core die, GT2 GPU, High Power
 
File:4 core hp gt2 skylake.svg|Quad-core die, GT2 GPU, High Power
 
File:6 core hp gt2 coffeelake.svg|Hexa-core die, GT2 GPU, High Power
 
</gallery>
 
 
{{clear}}
 
  
 
== Graphics ==
 
== Graphics ==
 
{{main|intel/microarchitectures/gen9.5|l1=Gen9.5}}
 
{{main|intel/microarchitectures/gen9.5|l1=Gen9.5}}
Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide a somewhat awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, and [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Coffee Lake's graphics are identical to Kaby Lake and have native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit).
+
Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, and [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Coffee Lake's graphics are identical to Kaby Lake and have native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit).
  
 
{| class="wikitable tc2 tc3"
 
{| class="wikitable tc2 tc3"
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| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
|-
 
|-
| {{intel|UHD Graphics 630}} || 12/24 || GT2 || {{intel|Coffee Lake S|S|l=core}} || - || colspan="2" style="text-align: center;" | '''1.0''' || style="text-align: center;" | '''12''' || style="text-align: center;" | '''N/A''' || style="text-align: center;" | '''5.1''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" | '''4.5''' || style="text-align: center;"  colspan="1" | '''2.1''' || style="text-align: center;" | '''2.0'''
+
| {{intel|UHD Graphics 630}} || 24 || GT2 || {{intel|Coffee Lake S|S|l=core}} || - || colspan="2" style="text-align: center;" | '''1.0''' || style="text-align: center;" | '''12''' || style="text-align: center;" | '''N/A''' || style="text-align: center;" | '''5.1''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" | '''4.5''' || style="text-align: center;"  colspan="1" | '''2.1''' || style="text-align: center;" | '''2.0'''
 
|}
 
|}
  
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==== Hardware Accelerated Video ====
 
==== Hardware Accelerated Video ====
 
{{coffee lake hardware accelerated video table}}
 
{{coffee lake hardware accelerated video table}}
 
== Power delivery ==
 
Despite using the same socket ({{intel|FCLGA-1151}}) Coffee Lake breaks compatibility with {{\\|Skylake (client)|Skylake}} and {{\\|Kaby Lake}} due to various enhancements to the power delivery of the processor in order to better handle the additional cores.
 
 
In order to improve the power delivery of the chip and support the higher package-level current delivered for the additional cores, Intel needed to increase the number of pins that go to the power rails of the die. Since there is a practical limit as to how much current each pin is capable of delivering, a large number of additional pins that were previously unused/reserved have also been allocated for this purpose. The new hexa-core parts have 38 higher amperage rating.
 
 
{| class="wikitable"
 
|-
 
! colspan="3" | Pin Changes
 
|-
 
! || Skylake/Kaby Lake || Coffee Lake
 
|-
 
! Socket || FCLGA-1151 v1 || FCLGA-1151 v2
 
|-
 
| Contacts || 1151 || 1151
 
|-
 
| Reserved Pins || 46 || 25 (-21)
 
|-
 
| VSS (Ground) || 377 || 391 (+14)
 
|-
 
| VCC (Power) || 128 || 146 (+18)
 
|-
 
| rowspan="8" | Core I<sub>cc</sub> || rowspan="2" | || 138 A (Hexa; 95 W)
 
|-
 
| 133 A (Hexa; 65 W)
 
|-
 
| 100 A (Quad; 91 W) || 100 A (Quad; 95 W)
 
|-
 
| 79 A (Quad; 65 W) || 79 A (Quad; 65 W)
 
|-
 
| 66 A (Quad; 35 W)
 
|-
 
| 58 A (Dual; 54 W)
 
|-
 
| 45 A (Dual; 51 W)
 
|-
 
| 40 A (Dual; 35 W)
 
|-
 
| Pinout || [[File:skylake pin diagram.png|350px]] || [[File:coffee lake pin diagram.png|350px]]
 
|}
 
  
 
== Die ==
 
== Die ==
Coffee Lake desktop and mobile come in 4, 6, and 8 cores. Each variant has its own die. The major components of the die are:
+
Coffee Lake desktop and mobile come and 4 and 6 cores. Each variant has its own die. The major components of the die are:
  
 
* System Agent
 
* System Agent
Line 548: Line 423:
 
* [[14 nm process|14 nm++ process]]
 
* [[14 nm process|14 nm++ process]]
 
* 11 metal layers
 
* 11 metal layers
* ~9.19 mm x ~16.28 mm
+
* 149 mm² die size
* ~149.6 mm² die size
 
 
* 6 CPU cores + 24 GPU EUs
 
* 6 CPU cores + 24 GPU EUs
  
  
: [[File:coffee lake die (hexa core).png|class=wikichip_ogimage|650px]]
+
: [[File:coffee lake die (hexa core).png|650px]]
 
 
 
 
: [[File:coffee lake die (hexa core) (annotated).png|650px]]
 
 
 
=== Octa-Core ===
 
* [[14 nm process|14 nm++ process]]
 
* 11 metal layers
 
* ~174 mm² die size
 
* 8 CPU cores + 24 GPU EUs
 
 
 
: [[File:coffee lake die (octa core).png|800px]]
 
  
  
: [[File:coffee lake die (octa core) (annotated).png|800px]]
+
: [[File:coffee lake die (quad core) (annotated).png|650px]]
  
 
=== Additional Shots ===
 
=== Additional Shots ===
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<gallery mode=slideshow>
 
<gallery mode=slideshow>
File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation core 6-core processor dies.
+
File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation core processor dies.
File:coffee lake r wafer.png|Coffee Lake Refresh silicon [[wafer]] with 9th generation core 8-core processor dies.
 
 
</gallery>
 
</gallery>
  
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  |userparam=22:21
 
  |userparam=22:21
 
  |mainlabel=-
 
  |mainlabel=-
|limit=200
 
 
}}
 
}}
 
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Coffee Lake]]}}
 
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Coffee Lake]]}}
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== Documents ==
 
== Documents ==
=== 8th Gen ===
 
 
* [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]]
 
* [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]]
 
* [[:File:8th-gen-intel-core-overview.pdf|8th generation Core product overview]]
 
* [[:File:8th-gen-intel-core-overview.pdf|8th generation Core product overview]]
 
* [[:File:8th-gen-intel-core-product-brief.pdf|8th generation core product brief]]
 
* [[:File:8th-gen-intel-core-product-brief.pdf|8th generation core product brief]]
* [[:File:8th-gen-intel-core-lineup-press-deck.pdf|8th generation core lineup]]
 
=== 9th Gen ===
 
* [[:File:9th-gen-core-desktop-brief.pdf|9th generation core product brief]]
 
  
 
== References ==
 
== References ==
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
 
* Intel 8th Generation Core announcement, Sept 25, 2017.
 
* Intel 8th Generation Core announcement, Sept 25, 2017.

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codenameCoffee Lake +
designerIntel +
first launchedOctober 5, 2017 +
full page nameintel/microarchitectures/coffee lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel + and dell +
microarchitecture typeCPU +
nameCoffee Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +