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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
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|introduction=October 5, 2017 | |introduction=October 5, 2017 | ||
|process=14 nm | |process=14 nm | ||
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|core name 2=Coffee Lake H | |core name 2=Coffee Lake H | ||
|core name 3=Coffee Lake S | |core name 3=Coffee Lake S | ||
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|predecessor=Kaby Lake | |predecessor=Kaby Lake | ||
|predecessor link=intel/microarchitectures/kaby lake | |predecessor link=intel/microarchitectures/kaby lake | ||
− | |successor= | + | |successor=Cannonlake |
− | |successor link=intel/microarchitectures/ | + | |successor link=intel/microarchitectures/cannonlake |
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}} | }} | ||
− | '''Coffee Lake''' ('''CFL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of [[2017]] and is manufactured on Intel's mature [[14 nm process]]. Coffee Lake features the first series of mainstream [[hexa-core]] processors from Intel | + | '''Coffee Lake''' ('''CFL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of [[2017]] and is manufactured on Intel's mature [[14 nm process]]. Coffee Lake features the first series of mainstream [[hexa-core]] processors from Intel. |
== Codenames == | == Codenames == | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Core !! Abbrev | + | ! Core !! Abbrev !! Description !! Graphics !! Target |
|- | |- | ||
− | | {{intel|Coffee Lake U|l=core}} || CFL-U | + | | {{intel|Coffee Lake U|l=core}} || CFL-U || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
|- | |- | ||
− | | {{intel|Coffee Lake H|l=core}} || CFL-H | + | | {{intel|Coffee Lake H|l=core}} || CFL-H || High-performance graphics || GT3e || Ultimate mobile performance, mobile workstations |
|- | |- | ||
− | | {{intel|Coffee Lake S|l=core}} || CFL-S | + | | {{intel|Coffee Lake S|l=core}} || CFL-S || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis |
|- | |- | ||
− | | {{intel|Coffee Lake | + | | {{intel|Coffee Lake X|l=core}} || CFL-X || Extreme Performance || || High performance desktops |
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|} | |} | ||
== Brands == | == Brands == | ||
− | Intel released Coffee Lake under | + | Intel released Coffee Lake under 3 main brand families: |
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
|- | |- | ||
− | ! rowspan="2" | Logo !! rowspan="2" | Family | + | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features |
|- | |- | ||
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | ||
|- | |- | ||
− | + | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || [[quad-core|Quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} | |
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− | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} | ||
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|- | |- | ||
− | | [[File:core | + | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | | [[File:core | + | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || Hexa || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} |
|} | |} | ||
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Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017. | Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017. | ||
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{{clear}} | {{clear}} | ||
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[[File:intel 14nm++.png|400px|right]] | [[File:intel 14nm++.png|400px|right]] | ||
{{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}} | {{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}} | ||
− | Coffee Lake is manufactured on [[Intel]]'s 3rd generation [[14 nm process]] called "14nm++". The process is the second enhanced version of the first which was used for the {{\\|Broadwell}} microarchitecture (first enhanced version was first used for {{\\|Kaby Lake}}). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides | + | Coffee Lake is manufactured on [[Intel]]'s 3rd generation [[14 nm process]] called "14nm++". The process is the second enhanced version of the first which was used for the {{\\|Broadwell}} microarchitecture (first enhanced version was first used for {{\\|Kaby Lake}}). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides 26% more performance for 52% less power. |
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− | Note that while both "14nm" and "14nm+" used the same transistor geometry, the "14nm++" actually uses a more relaxed contacted poly pitch of 84 nm (from previously 70nm). | + | Note that while both "14nm" and "14nm+" used the same transistor geometry, the "14nm++" actually uses a more relaxed contacted poly pitch of 84 nm (from previously 70nm). It's unknown what kind of effect this has on the overall density, if any. |
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{{clear}} | {{clear}} | ||
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=== CPUID === | === CPUID === | ||
− | {| class="wikitable tc1 tc2 tc3 tc4 | + | {| class="wikitable tc1 tc2 tc3 tc4" |
− | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | + | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model |
|- | |- | ||
− | | rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || | + | | rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x? || 0xE? |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model ??? |
|- | |- | ||
− | | rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || | + | | rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x? || 0x? |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model ??? |
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|} | |} | ||
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== Architecture == | == Architecture == | ||
[[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]] | [[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]] | ||
− | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50% | + | While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50%, enabling much higher multi-threaded performance. The enhanced manufacturing process should allowed Coffee Lake chips to be highly [[overclockable]]. |
=== Key changes from {{\\|Kaby Lake}}=== | === Key changes from {{\\|Kaby Lake}}=== | ||
* Enhanced "14nm++" process results in higher turbo frequencies | * Enhanced "14nm++" process results in higher turbo frequencies | ||
− | * IPC | + | * Same IPC as Skylake (i.e. performance/[[MHz]] is unchanged) |
− | * System | + | * System Architect |
− | ** 50% more [[physical core|cores]] | + | ** 50% more [[physical core|cores]] |
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* Chipset | * Chipset | ||
− | ** {{intel|Union Point|200 Series chipset|l=chipset}} → | + | ** {{intel|Union Point|200 Series chipset|l=chipset}} → 300 Series chipset (Cannonlake PCH) |
+ | *** Integrated Programmable (Open FW SDK) Quad-Core Audio DSP | ||
+ | *** Soundwire Digital Audio Interface | ||
*** Integrated USB 3.1 (10 Gib/s) | *** Integrated USB 3.1 (10 Gib/s) | ||
**** Up to 6 ports | **** Up to 6 ports | ||
− | *** Integrated | + | *** Integrated Intel wireless controller ([[IEEE 802.11ac]]) |
*** Integrated SDXC 3.0 controller | *** Integrated SDXC 3.0 controller | ||
+ | *** Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support | ||
+ | *** C10 & S0ix Support for Modern Standby | ||
* Memory | * Memory | ||
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** {{intel|Gen 9.5|l=arch}} GPUs (No Change) | ** {{intel|Gen 9.5|l=arch}} GPUs (No Change) | ||
** HD Graphics 6x0 '''→''' UHD Graphics 6x0 (Branding change only) | ** HD Graphics 6x0 '''→''' UHD Graphics 6x0 (Branding change only) | ||
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*** {{intel|HD Graphics 630}} '''→''' {{intel|UHD Graphics 630}} (No change) | *** {{intel|HD Graphics 630}} '''→''' {{intel|UHD Graphics 630}} (No change) | ||
* Families | * Families | ||
− | + | ** {{intel|Core i3}} gained 100% more [[physical core|cores]] (4, from 2) but dropped {{intel|hyper-threading}} support | |
− | + | ** {{intel|Core i5}} gained 50% more cores (6, from 4) | |
− | + | ** {{intel|Core i7}} gained 50% more cores (6, from 4) | |
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− | ** {{intel|Core i3}} | ||
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− | ** {{intel|Core i5}} | ||
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− | ** {{intel|Core i7}} | ||
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=== Memory Hierarchy === | === Memory Hierarchy === | ||
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**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
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**** fixed partition | **** fixed partition | ||
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= --> | <!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= --> | ||
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== Core == | == Core == | ||
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{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | {{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}} | ||
Coffee Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | Coffee Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}. | ||
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==== Scheduler Ports & Execution Units ==== | ==== Scheduler Ports & Execution Units ==== | ||
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<tr><th>Port 2</th><td>Load, AGU</td></tr> | <tr><th>Port 2</th><td>Load, AGU</td></tr> | ||
<tr><th>Port 3</th><td>Load, AGU</td></tr> | <tr><th>Port 3</th><td>Load, AGU</td></tr> | ||
− | <tr><th>Port 4</th><td>Store</td></tr> | + | <tr><th>Port 4</th><td>Store, AGU</td></tr> |
<tr><th>Port 7</th><td>AGU</td></tr> | <tr><th>Port 7</th><td>AGU</td></tr> | ||
</table> | </table> | ||
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|- | |- | ||
|colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included. | |colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included. | ||
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|} | |} | ||
== Die == | == Die == | ||
− | Coffee Lake desktop and mobile come | + | Coffee Lake desktop and mobile come and 4 and 6 cores. Each variant has its own die. The major components of the die are: |
* System Agent | * System Agent | ||
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* [[14 nm process|14 nm++ process]] | * [[14 nm process|14 nm++ process]] | ||
* 11 metal layers | * 11 metal layers | ||
− | * | + | * 149 mm² die size |
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* 6 CPU cores + 24 GPU EUs | * 6 CPU cores + 24 GPU EUs | ||
− | : [[File:coffee lake die (hexa core).png | + | : [[File:coffee lake die (hexa core).png|650px]] |
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− | : [[File:coffee lake die ( | + | : [[File:coffee lake die (quad core) (annotated).png|650px]] |
=== Additional Shots === | === Additional Shots === | ||
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<gallery mode=slideshow> | <gallery mode=slideshow> | ||
− | File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation | + | File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation core processor dies. |
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</gallery> | </gallery> | ||
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|userparam=22:21 | |userparam=22:21 | ||
|mainlabel=- | |mainlabel=- | ||
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}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Coffee Lake]]}} | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Coffee Lake]]}} | ||
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== Documents == | == Documents == | ||
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* [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]] | * [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]] | ||
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== References == | == References == | ||
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | * Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | ||
* Intel 8th Generation Core announcement, Sept 25, 2017. | * Intel 8th Generation Core announcement, Sept 25, 2017. |
Facts about "Coffee Lake - Microarchitectures - Intel"
codename | Coffee Lake + |
designer | Intel + |
first launched | October 5, 2017 + |
full page name | intel/microarchitectures/coffee lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + and dell + |
microarchitecture type | CPU + |
name | Coffee Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |