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=== Block Diagram === | === Block Diagram === | ||
− | ==== Entire SoC Overview ==== | + | ==== Entire SoC Overview (dual) ==== |
[[File:cannon lake soc block diagram.svg|800px]] | [[File:cannon lake soc block diagram.svg|800px]] | ||
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==== Gen11 Graphics ==== | ==== Gen11 Graphics ==== | ||
See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}. | See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}. | ||
+ | |||
+ | === Block Diagram === | ||
+ | |||
+ | ====== Entire SoC Overview (dual) ====== | ||
+ | [[File:cannon lake soc block diagram (dual).svg|800px]] | ||
+ | |||
+ | ==== Individual Core ==== | ||
+ | {{empty section}} | ||
+ | |||
+ | ==== Gen10 ==== | ||
+ | See {{intel|Gen10#Gen10|l=arch}}. | ||
== Die == | == Die == |
Facts about "Cannon Lake - Microarchitectures - Intel"
codename | Cannon Lake + |
core count | 2 + |
designer | Intel + |
first launched | May 15, 2018 + |
full page name | intel/microarchitectures/cannon lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cannon Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |