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==== Physical layout ==== | ==== Physical layout ==== | ||
[[File:bonnell die size areas.svg|right|500px]][[File:bonnell die size areas 2.svg|right|500px]] | [[File:bonnell die size areas.svg|right|500px]][[File:bonnell die size areas 2.svg|right|500px]] | ||
− | The Atom design team was considerably smaller than Intel's typical design teams which forced them to work in a slightly different way. The design team used a methodology they described as a "sea of Functional Unit Block" (FUBs) where by all cluster hierarchies (including unit-level hierarchies) are flattened at the chip level. This development methodology allowed for faster iteration. The various FUB designs were divided among the team members allowing them to handle the design in a more manageable way. All in all, Bonnell's physical database consisted of 205 unique FUBs interlinked via 41,000 FUB-to-FUB interconnects. Bonnell is manufactured on [[Intel]]'s [[45 nm process]]. 91% of the FUBs using pre-characterized [[standard cells]] (45% structured data-path and 46% fully synthesized random logic blocks) with only the remaining 9% being [[full-custom]] blocks | + | The Atom design team was considerably smaller than Intel's typical design teams which forced them to work in a slightly different way. The design team used a methodology they described as a "sea of Functional Unit Block" (FUBs) where by all cluster hierarchies (including unit-level hierarchies) are flattened at the chip level. This development methodology allowed for faster iteration. The various FUB designs were divided among the team members allowing them to handle the design in a more manageable way. All in all, Bonnell's physical database consisted of 205 unique FUBs interlinked via 41,000 FUB-to-FUB interconnects. Bonnell is manufactured on [[Intel]]'s [[45 nm process]]. 91% of the FUBs using pre-characterized [[standard cells]] (45% structured data-path and 46% fully synthesized random logic blocks) with only the remaining 9% being [[full-custom]] blocks. |
{| class="wikitable sortable" | {| class="wikitable sortable" |
Facts about "Bonnell - Microarchitectures - Intel"
codename | Bonnell + |
core count | 1 + and 2 + |
designer | Intel + |
first launched | March 2, 2008 + |
full page name | intel/microarchitectures/bonnell + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Bonnell + |
phase-out | 2011 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 16 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |