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Because Bonnell has support for {{intel|Hyper-Threading}}, Intel's brand name for their own [[simultaneous multithreading]] technology, a number of modifications had to be done. The [[prefetch buffer]] and the [[instruction queue]] have been duplicated for each thread. | Because Bonnell has support for {{intel|Hyper-Threading}}, Intel's brand name for their own [[simultaneous multithreading]] technology, a number of modifications had to be done. The [[prefetch buffer]] and the [[instruction queue]] have been duplicated for each thread. | ||
===== Branch predictor ===== | ===== Branch predictor ===== | ||
− | No aggressive speculative execution is done in Bonnell, however it does implements a light-weight | + | No aggressive speculative execution is done in Bonnell, however it does implements a light-weight [[branch predictor]] consisting of a [[two-level adaptive predictor]] with a 12-bit global history table. The pattern history table has 4096 entries and is [[competitively shared]] between threads. The branch buffer target has 128 entries (4-way by 32 sets). While [[unconditional jumps]] are not recorded in the table, [[always-taken]] and [[never-taken]] jumps do. |
The branch-misprediction penalty is 11 to 13 cycles. Some of the rare or complex x86 instructions will detour into a microcode sequencer for decoding, necessitating two additional clock cycles. Additionally there is a roughly 7 cycle penalty for correctly predicted branches but no target can be predicted because of a missing [[branch target buffer]] (BTB) entry. Bonnell return stack buffer is 8-entry deep. | The branch-misprediction penalty is 11 to 13 cycles. Some of the rare or complex x86 instructions will detour into a microcode sequencer for decoding, necessitating two additional clock cycles. Additionally there is a roughly 7 cycle penalty for correctly predicted branches but no target can be predicted because of a missing [[branch target buffer]] (BTB) entry. Bonnell return stack buffer is 8-entry deep. |
Facts about "Bonnell - Microarchitectures - Intel"
codename | Bonnell + |
core count | 1 + and 2 + |
designer | Intel + |
first launched | March 2, 2008 + |
full page name | intel/microarchitectures/bonnell + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Bonnell + |
phase-out | 2011 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 16 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |