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** L2 Cache:
 
** L2 Cache:
 
*** 512 KiB 8-way set associative
 
*** 512 KiB 8-way set associative
*** ECC support
+
*** ECC
 
*** Shrinkable from 512 KiB to 128 KiB (2-way)
 
*** Shrinkable from 512 KiB to 128 KiB (2-way)
*** 64-bit cache line
 
 
*** Per core
 
*** Per core
 
** Tag/[[Least Recently Used|LRU]]/State bit
 
** Tag/[[Least Recently Used|LRU]]/State bit
Line 253: Line 252:
  
 
Note that the L1 cache for data and instructions were originally both 32 KiB (8-way), however due to power restrictions, the L1d$ was later reduced to 24 KiB.
 
Note that the L1 cache for data and instructions were originally both 32 KiB (8-way), however due to power restrictions, the L1d$ was later reduced to 24 KiB.
 
* TLB
 
** ITLB
 
*** 32-entry
 
*** fully associative
 
** DTLB
 
*** 4 KiB PAges
 
**** 64-entry TLB
 
***** 4-way set associative
 
**** 16-entry micro-TLB
 
***** fully associative
 
***** duplicated for each thread
 
**** 16-entry PDE cache
 
*****fully associative
 
*** Large Pages
 
**** 8 entries, 4-way set associative
 
  
 
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=== Overview ===

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