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** L2 Cache: | ** L2 Cache: | ||
*** 512 KiB 8-way set associative | *** 512 KiB 8-way set associative | ||
− | *** ECC | + | *** ECC |
*** Shrinkable from 512 KiB to 128 KiB (2-way) | *** Shrinkable from 512 KiB to 128 KiB (2-way) | ||
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*** Per core | *** Per core | ||
** Tag/[[Least Recently Used|LRU]]/State bit | ** Tag/[[Least Recently Used|LRU]]/State bit | ||
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Note that the L1 cache for data and instructions were originally both 32 KiB (8-way), however due to power restrictions, the L1d$ was later reduced to 24 KiB. | Note that the L1 cache for data and instructions were originally both 32 KiB (8-way), however due to power restrictions, the L1d$ was later reduced to 24 KiB. | ||
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=== Overview === | === Overview === |
Facts about "Bonnell - Microarchitectures - Intel"
codename | Bonnell + |
core count | 1 + and 2 + |
designer | Intel + |
first launched | March 2, 2008 + |
full page name | intel/microarchitectures/bonnell + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Bonnell + |
phase-out | 2011 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 16 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |