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Latest revision | Your text | ||
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{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name= | + | |name=Whiskey Lake |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |introduction= | + | |introduction=June, 2018 |
|process=14 nm | |process=14 nm | ||
|cores=2 | |cores=2 | ||
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|contemporary=Coffee Lake | |contemporary=Coffee Lake | ||
|contemporary link=intel/microarchitectures/coffee lake | |contemporary link=intel/microarchitectures/coffee lake | ||
− | |contemporary 2= | + | |contemporary 2=Cannon Lake |
− | |contemporary 2 | + | |contemporary 2 link=intel/microarchitectures/cannon lake |
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}} | }} | ||
− | '''Amber Lake''' | + | '''Amber Lake''' is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for ultra-low power mobile devices, launched concurrently with {{\\|Whiskey Lake}}. |
== Codenames == | == Codenames == | ||
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=== CPUID === | === CPUID === | ||
− | {| class="wikitable tc1 tc2 tc3 tc4 | + | {| class="wikitable tc1 tc2 tc3 tc4" |
− | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | + | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model |
|- | |- | ||
− | | rowspan="2" | {{intel|Amber Lake Y|Y|l=core}} || 0 || 0x6 || | + | | rowspan="2" | {{intel|Amber Lake Y|Y|l=core}} || 0 || 0x6 || ? || ? |
|- | |- | ||
− | | colspan=" | + | | colspan="4" | Family 6 Model ? |
|} | |} | ||
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== Overview == | == Overview == | ||
{{empty section}} | {{empty section}} | ||
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Facts about "Amber Lake - Microarchitectures - Intel"
codename | Amber Lake + |
core count | 2 + |
designer | Intel + |
first launched | April 2018 + |
full page name | intel/microarchitectures/amber lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Amber Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |