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{{intel title|Mesh Interconnect Architecture}} | {{intel title|Mesh Interconnect Architecture}} | ||
− | Intel's '''mesh interconnect architecture''' is a [[multi-core]] system | + | Intel's '''mesh interconnect architecture''' is a [[multi-core]] system interconnect architecture that implements a 2-dimensional array of half rings. Their mesh architecture has replaced the {{intel|ring interconnect architecture}} in the server and [[HPC]] markets. |
== History == | == History == | ||
− | Since the late 2000s, Intel has used a {{intel|ring interconnect architecture}} in order to interconnect multiple [[physical cores]] together efficiently. Throughout the 2010s as the number of cores on Intel's high-end models continue to increase, the ring reached fairly problematic scaling issues, particularly in the area of bandwidth and latency. To | + | Since the late 2000s, Intel has used a {{intel|ring interconnect architecture}} in order to interconnect multiple [[physical cores]] together efficiently. Throughout the 2010s as the number of cores on Intel's high-end models continue to increase, the ring reached fairly problematic scaling issues, particularly in the area of bandwidth and latency. To significant mitigate those bottlenecks, Intel introduced a new mesh interconnect architecture which implemented a mesh networking topology in order to reduce the latency between nodes and increase the bandwidth. |
− | + | In June [[2016]], Intel launched new {{intel|Xeon Phi}} {{intel|mic architecture|MIC}} microprocessors based on {{intel|Knights Landing|l=arch}} which was Intel's first microarchitecture to implement the new interconnect architecture. In mid-[[2017]] Intel launched the {{intel|Skylake (server)|Skylake server microarchitecture|l=arch}} which featured also featured the mesh interconnect. This microarchitecture is found in their server ({{intel|Xeon Scalable}}) microprocessors and the {{intel|Core i7}} and {{intel|Core i9}} HEDT parts. | |
== Overview == | == Overview == | ||
− | Intel's mesh interconnect architecture consists of a number of | + | Intel's mesh interconnect architecture consists of a number of tightly coupled concepts: |
* '''Mesh''' - the fabric, a 2-dimensional array of half rings forming a system-wide interconnect grid | * '''Mesh''' - the fabric, a 2-dimensional array of half rings forming a system-wide interconnect grid | ||
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</div> | </div> | ||
{{clear}} | {{clear}} | ||
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== Operations == | == Operations == | ||
A packet follows a simple routing algorithm: | A packet follows a simple routing algorithm: | ||
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=== Knights Landing === | === Knights Landing === | ||
{{main|intel/microarchitectures/knights_landing#Memory_Hierarchy|l1=Knights Landing}} | {{main|intel/microarchitectures/knights_landing#Memory_Hierarchy|l1=Knights Landing}} | ||
− | + | {{empty section}} | |
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=== Skylake (server) === | === Skylake (server) === | ||
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* IEEE Hot Chips 27 Symposium (HCS) 2015. | * IEEE Hot Chips 27 Symposium (HCS) 2015. | ||
* IEEE ISSCC 2018 | * IEEE ISSCC 2018 | ||
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