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{{intel title|Skylake SP|core}} | {{intel title|Skylake SP|core}} | ||
{{core | {{core | ||
− | |name=Skylake SP | + | | name = Skylake SP |
− | |image=skylake sp (basic).png | + | | image = skylake sp (basic).png |
− | |image 2=skylake-sp (hfi).png | + | | caption = Skylake SP, Regular |
− | |caption 2=Skylake SP, with HFI | + | | image size = |
− | |developer=Intel | + | | image 2 = skylake-sp (hfi).png |
− | |manufacturer=Intel | + | | caption 2 = Skylake SP, with HFI |
− | |first announced=May 4, 2017 | + | | image 2 size = |
− | |first launched=July 11, 2017 | + | | developer = Intel |
− | |isa=x86-64 | + | | manufacturer = Intel |
− | |microarch=Skylake | + | | first announced = May 4, 2017 |
− | + | | first launched = July 11, 2017 | |
− | + | | isa = x86-64 | |
− | |word=64 bit | + | | microarch = Skylake |
− | |proc=14 nm | + | | word = 64 bit |
− | |tech=CMOS | + | | proc = 14 nm |
− | |clock min=2.0 GHz | + | | tech = CMOS |
− | |clock max=3.6 GHz | + | | clock min = 2.0 GHz |
− | |package | + | | clock max = 3.6 GHz |
− | |predecessor=Broadwell EP | + | | package = FCLGA-3647 |
− | |predecessor link=intel/cores/broadwell ep | + | | socket = LGA-3647 |
− | |predecessor 2=Broadwell EX | + | |
− | |predecessor 2 link=intel/cores/broadwell ex | + | | succession = Yes |
− | |successor=Cascade Lake SP | + | | predecessor = Broadwell EP |
− | |successor link=intel/cores/cascade lake sp | + | | predecessor link = intel/cores/broadwell ep |
− | + | | predecessor 2 = Broadwell EX | |
− | + | | predecessor 2 link = intel/cores/broadwell ex | |
− | + | | successor = Cascade Lake SP | |
+ | | successor link = intel/cores/cascade lake sp | ||
}} | }} | ||
− | '''Skylake SP''' ('''{{intel|Skylake|l=arch}} Scalable Performance''') is the code name for Intel's series of server [[multiprocessors]] based on the {{intel | + | '''Skylake SP''' ('''{{intel|Skylake|l=arch}} Scalable Performance''') is the code name for Intel's series of server [[multiprocessors]] based on the {{intel|Skylake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as a successor to both {{intel|Broadwell EX|l=core}} and {{intel|Broadwell EP|l=core}}. These chips support up to 8-way multiprocessing, up to [[28 cores]], and incorporate a new {{x86|AVX-512}} [[x86]] {{x86|extension}}. Skylake SP-based chips are manufactured on an enhanced [[14 nm process|14nm+ process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. Skylake SP-based models are branded as the [[processor families]]: {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}. |
== Overview == | == Overview == | ||
− | Skylake SP processors are based on Intel's {{intel | + | Skylake SP processors are based on Intel's {{intel|Skylake|l=arch}} server configuration which incorporates a very large number of enhancements and improvements over its predecessor. Those processors support between two and eight-way multi-processing (the exact support depends on the Xeon family) and with all models supporting hex-chanel 768 GiB of DDR4 ECC memory or 1.5 GiB for extended memory models. |
− | Skylake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|skylake | + | Skylake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|skylake#Scalability|Skylake § Scalability|l=arch}}). |
=== Common Features === | === Common Features === | ||
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* Hexa-channel memory | * Hexa-channel memory | ||
− | ** 768 GiB / 1.5 | + | ** Up to 768 GiB / 1.5 GiB for extended memory variants |
** UP to DDR4-2666 MT/s | ** UP to DDR4-2666 MT/s | ||
** [[ECC]] support | ** [[ECC]] support | ||
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* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). | ||
** Silver and up also have {{intel|Hyper-Threading}} and {{intel|Turbo Boost}} | ** Silver and up also have {{intel|Hyper-Threading}} and {{intel|Turbo Boost}} | ||
− | ** Gold and up also have Node Controller Support and | + | ** Gold and up also have Node Controller Support and Integrated Omni-Path Architecture |
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{{clear}} | {{clear}} |
Facts about "Skylake SP - Cores - Intel"
chipset | Lewisburg + |
designer | Intel + |
first announced | May 4, 2017 + |
first launched | July 11, 2017 + |
instance of | core + |
isa | x86-64 + |
main image | + and + |
main image caption | Skylake SP, with HFI + |
manufacturer | Intel + |
microarchitecture | Skylake (server) + |
name | Skylake SP + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket P + and LGA-3647 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |