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{{intel title|Skylake S|core}} | {{intel title|Skylake S|core}} | ||
{{core | {{core | ||
− | |name=Skylake S | + | | name = Skylake S |
− | |image=skylake s (front).png | + | | image = skylake s (front).png |
− | |image size=250px | + | | image size = 250px |
− | |image 2=skylake s (back).png | + | | image 2 = skylake s (back).png |
− | |image 2 size=250px | + | | image 2 size = 250px |
− | |developer=Intel | + | | developer = Intel |
− | |manufacturer=Intel | + | | manufacturer = Intel |
− | |first announced=September 1, 2015 | + | | first announced = September 1, 2015 |
− | |first launched=September 27, 2015 | + | | first launched = September 27, 2015 |
− | |isa=x86-64 | + | | isa = x86-64 |
− | |microarch=Skylake | + | | microarch = Skylake |
− | |word=64 bit | + | | word = 64 bit |
− | |proc=14 nm | + | | proc = 14 nm |
− | |tech=CMOS | + | | tech = CMOS |
− | |clock min=1,900 MHz | + | | clock min = 1,900 MHz |
− | |clock max=4, | + | | clock max = 4,00 MHz |
− | | | + | | package = FCLGA-1151 |
− | | | + | | socket = LGA-1151 |
− | |predecessor | + | |
− | |predecessor | + | | succession = Yes |
− | |successor=Kaby Lake S | + | | predecessor = Broadwell S |
− | |successor link=intel/cores/kaby lake s | + | | predecessor link = intel/cores/broadwell s |
− | + | | successor = Kaby Lake S | |
− | + | | successor link = intel/cores/kaby lake s | |
− | |||
}} | }} | ||
− | '''Skylake S''' ('''SKL-S''') is the name of the core for [[Intel]]'s mainstream performance line of processors based on the {{intel|Skylake|l=arch}} microarchitecture serving as a successor to {{intel| | + | '''Skylake S''' ('''SKL-S''') is the name of the core for [[Intel]]'s mainstream performance line of processors based on the {{intel|Skylake|l=arch}} microarchitecture serving as a successor to {{intel|Broadwell S|l=core}}. These chips are primarily targeted towards desktop performance to value computers, AiOs, and minis. Skylake S processors are fabricated on Intel's [[14 nm process]] and provide {{intel|skylake#Key_changes_from_Broadwell|a considerable number of changes|l=arch}} from the Broadwell models. |
== Overview == | == Overview == | ||
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* 16x PCIe (4 of the 20 are used by the bus as described above) | * 16x PCIe (4 of the 20 are used by the bus as described above) | ||
* [[dual-core|2]] to [[quad-core|4]] core with 2 to 8 threads (not all S models support {{intel|Hyper-Threading}}) | * [[dual-core|2]] to [[quad-core|4]] core with 2 to 8 threads (not all S models support {{intel|Hyper-Threading}}) | ||
− | * Everything up to | + | * Everything up to SSE4.2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES) (not all S models support {{x86|AVX2}}) |
* Graphics | * Graphics | ||
− | ** {{intel|HD Graphics 510}} ({{intel|Gen9|l=arch}} GT1) or {{intel|HD Graphics 530}} ({{intel|Gen9|l=arch}} GT2) | + | ** {{intel|HD Graphics 510}} ({{intel|Gen9.5|l=arch}} GT1) or {{intel|HD Graphics 530}} ({{intel|Gen9.5|l=arch}} GT2) |
** Base frequency of 350 MHz | ** Base frequency of 350 MHz | ||
** Burst frequency of 1-1.15 GHz | ** Burst frequency of 1-1.15 GHz |
Facts about "Skylake S - Cores - Intel"
designer | Intel + |
first announced | September 1, 2015 + |
first launched | September 27, 2015 + |
instance of | core + |
isa | x86-64 + |
main image | + and + |
manufacturer | Intel + |
microarchitecture | Skylake + |
name | Skylake S + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |