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== Overview == | == Overview == | ||
− | Kaby Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Note that some models (the Iris [[IGP]]s) are actually a 3 dice chip configuration since they incorporate an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Kaby Lake U processors use {{intel|BGA-1356|Socket BGA-1356}} and all Iris models include 64 MiB of | + | Kaby Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Note that some models (the Iris [[IGP]]s) are actually a 3 dice chip configuration since they incorporate an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Kaby Lake U processors use {{intel|BGA-1356|Socket BGA-1356}} and all Iris models include 64 MiB of 4th level cache (See {{intel|Crystal Well}}). |
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Facts about "Kaby Lake U - Cores - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Kaby Lake U - Cores - Intel#package + |
designer | Intel + |
first announced | August 30, 2016 + |
first launched | August 30, 2016 + |
instance of | core + |
isa | x86-64 + |
main image | + and + |
main image caption | 3-die config Iris Plus KBL-U (with OPC) + and 2-die config KBL-U + |
manufacturer | Intel + |
microarchitecture | Kaby Lake + |
name | Kaby Lake U + |
package | FCBGA-1356 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |