From WikiChip
Editing intel/cores/kaby lake r
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 23: | Line 23: | ||
|predecessor=Kaby Lake U | |predecessor=Kaby Lake U | ||
|predecessor link=intel/cores/kaby lake u | |predecessor link=intel/cores/kaby lake u | ||
− | |successor= | + | |successor=Coffee Lake U |
− | |successor link=intel/cores/ | + | |successor link=intel/cores/coffee lake u |
− | |||
− | |||
}} | }} | ||
'''Kaby Lake R''' ('''KBL-R''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a refresh to {{intel|Kaby Lake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Kaby Lake R processors are fabricated on Intel's 2nd generation enhanced [[14 nm lithography process|14nm+ process]] and feature double the core count of the previous generation. | '''Kaby Lake R''' ('''KBL-R''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a refresh to {{intel|Kaby Lake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Kaby Lake R processors are fabricated on Intel's 2nd generation enhanced [[14 nm lithography process|14nm+ process]] and feature double the core count of the previous generation. | ||
− | Although those microprocessors are still based on {{intel|Kaby Lake|l=arch}}, Intel has branded them as 8th Generation Core | + | Although those microprocessors are still based on {{intel|Kaby Lake|l=arch}}, Intel has branded them as 8th Generation Core. |
== Overview == | == Overview == | ||
Line 47: | Line 45: | ||
* Support [[AHCI]], [[High Definition Audio]], 6x [[USB 3.0]] ports, 10x [[USB 2.0]] ports, 4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]] | * Support [[AHCI]], [[High Definition Audio]], 6x [[USB 3.0]] ports, 10x [[USB 2.0]] ports, 4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]] | ||
* Graphics | * Graphics | ||
− | ** {{intel| | + | ** {{intel|HD Graphics 620}} ({{intel|Gen9.5|l=arch}} GT2) |
** 3 independent displays supported | ** 3 independent displays supported | ||
** Base frequency of 300 MHz | ** Base frequency of 300 MHz | ||
Line 53: | Line 51: | ||
{{clear}} | {{clear}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Kaby Lake R Processors == | == Kaby Lake R Processors == |
Facts about "Kaby Lake R - Cores - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Kaby Lake R - Cores - Intel#package + |
designer | Intel + |
first announced | August 21, 2017 + |
first launched | August 21, 2017 + |
instance of | core + |
isa | x86-64 + |
main image | + and + |
main image caption | Package front side + and Package back side + |
manufacturer | Intel + |
microarchitecture | Kaby Lake + |
name | Kaby Lake R + |
package | FCBGA-1356 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |