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== Overview == | == Overview == | ||
− | Kaby Lake H based processors are a 2-chip solution - the [[microprocessor]] and the [[chipset]]. Kaby Lake H are {{intel| | + | Kaby Lake H based processors are a 2-chip solution - the [[microprocessor]] and the [[chipset]]. Kaby Lake H are {{intel|socket BGA-1440}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake H|l=core}}) {{intel|Sunrise Point}} via a firmware upgrade. The microprocessor is connected to the chipset via 4 of the chip's 20 PCIe lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. |
=== Common Features === | === Common Features === |
Facts about "Kaby Lake H - Cores - Intel"
designer | Intel + |
first announced | January 3, 2017 + |
first launched | January 3, 2017 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | + and + |
manufacturer | Intel + |
microarchitecture | Kaby Lake + |
name | Kaby Lake H + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |