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|predecessor=Avoton | |predecessor=Avoton | ||
|predecessor link=intel/cores/avoton | |predecessor link=intel/cores/avoton | ||
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|succession=Yes | |succession=Yes | ||
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− | '''Denverton''' | + | '''Denverton''' is the core name for [[Intel]]'s ultra-low power series of microserver [[system on chip]]s serving as a successor to {{\\|Avoton}}. Those chips are aimed at a wide array of markets such as ULP servers, networking, storage, edge, and [[IoT]]. Denverton chips are manufactured on Intel's [[14 nm process]] and are based on the {{intel|Goldmont|l=arch}} microarchitecture. |
− | == | + | == Features == |
− | + | {{empty section}} | |
=== Common Features === | === Common Features === | ||
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== Denverton Processors == | == Denverton Processors == | ||
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{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable tc6 tc7 tc8 tc15 | + | <table class="comptable sortable tc6 tc7 tc8 tc14 tc15"> |
− | <tr class="comptable-header"><th> </th><th colspan=" | + | <tr class="comptable-header"><th> </th><th colspan="14">List of Denverton Processors</th></tr> |
− | <tr class="comptable-header"><th> </th><th colspan="9">Main processor</th><th colspan="2">Cache</th><th | + | <tr class="comptable-header"><th> </th><th colspan="9">Main processor</th><th colspan="2">Cache</th><th>Memory</th><th colspan="2">Feature Diff</th></tr> |
− | {{comp table header 1|cols=Price, Family, Process, Launched, Cores, Threads, %TDP, %Frequency, %Turbo, %L1, %L2, Memory Type | + | {{comp table header 1|cols=Price, Family, Process, Launched, Cores, Threads, %TDP, %Frequency, %Turbo, %L1, %L2, Memory Type, ECC, {{intel|HyperThreading|HT}}}} |
− | + | {{#ask: [[Category:microprocessor models by intel]] [[core name::Denverton]] | |
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− | }} | ||
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− | {{#ask: [[Category:microprocessor models by intel]] [[core name::Denverton | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
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|?base frequency | |?base frequency | ||
|?turbo frequency (1 core) | |?turbo frequency (1 core) | ||
− | |?l1$ size | + | |?l1$ size |
|?l2$ size | |?l2$ size | ||
|?supported memory type | |?supported memory type | ||
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|?has ecc memory support | |?has ecc memory support | ||
− | |?has | + | |?has simultaneous multithreading |
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|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=16:15 |
|mainlabel=- | |mainlabel=- | ||
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}} | }} | ||
{{comp table count|col=10|ask=[[Category:microprocessor models by intel]][[core name::Denverton]]}} | {{comp table count|col=10|ask=[[Category:microprocessor models by intel]][[core name::Denverton]]}} | ||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
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== See also == | == See also == |
Facts about "Denverton - Cores - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Denverton - Cores - Intel#package + |
designer | Intel + |
first announced | June 1, 2016 + |
first launched | February 22, 2017 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | + |
main image caption | FCBGA-1310 Front + |
manufacturer | Intel + |
microarchitecture | Goldmont + |
name | Denverton + |
package | FCBGA-1310 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |