From WikiChip
Editing intel/cores/denverton
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 28: | Line 28: | ||
== Overview == | == Overview == | ||
− | Denverton-based chips are a complete system on a chip designed for microserver application, network, storage and [[internet of things]]. Those chips are based on the {{intel|Goldmont|l=arch}} microarchitecture and are manufactured on Intel's [[14 nm process]]. Denverton incorporate anywhere from 2 to 16 cores ranging from 9 to 32 Watts TDP and use the {{intel|FCBGA-1310}} packaging. Those SoCs come with 6 to 20 High-Speed Input/Output (HSIO) lanes which are highly configurable lanes that allow their intended purpose (e.g., SATA, PCIe, USB) to be setup by the user in the [[BIOS]]. The exact amount of each that can be allocated is model-dependent | + | Denverton-based chips are a complete system on a chip designed for microserver application, network, storage and [[internet of things]]. Those chips are based on the {{intel|Goldmont|l=arch}} microarchitecture and are manufactured on Intel's [[14 nm process]]. Denverton incorporate anywhere from 2 to 16 cores ranging from 9 to 32 Watts TDP and use the {{intel|FCBGA-1310}} packaging. Those SoCs come with 6 to 20 High-Speed Input/Output (HSIO) lanes which are highly configurable lanes that allow their intended purpose (e.g., SATA, PCIe, USB) to be setup by the user in the [[BIOS]]. The exact amount of each that can be allocated is model-dependent. Additionally, each model have two to four dedicated integrated Ethernet adapters supporting up [[10 GbE]]. Depending on the exact model, some also have integrated {{intel|QuickAssist}} Technology which offers the ability to off-load cryptography and compression tasks to a separate dedicated engine on-die. |
=== Common Features === | === Common Features === | ||
All Denverton models have the following features: | All Denverton models have the following features: |
Facts about "Denverton - Cores - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Denverton - Cores - Intel#package + |
designer | Intel + |
first announced | June 1, 2016 + |
first launched | February 22, 2017 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | + |
main image caption | FCBGA-1310 Front + |
manufacturer | Intel + |
microarchitecture | Goldmont + |
name | Denverton + |
package | FCBGA-1310 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |