From WikiChip
Editing intel/cores/coffee lake u

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 15: Line 15:
 
|clock min=2,300 MHz
 
|clock min=2,300 MHz
 
|clock max=3,000 MHz
 
|clock max=3,000 MHz
−
|package module 1={{packages/intel/fcbga-1528}}
+
|predecessor=Kaby Lake R
−
|predecessor=Kaby Lake U
+
|predecessor link=intel/cores/kaby lake r
−
|predecessor link=intel/cores/kaby lake u
+
|successor=Ice Lake U
−
|successor=Comet Lake U
+
|successor link=intel/cores/ice lake u
−
|successor link=intel/cores/comet lake u
+
|contemporary=Cannon Lake U
−
|successor 2=Ice Lake U
+
|contemporary link=intel/cores/cannon lake u
−
|successor 2 link=intel/cores/ice lake u
+
|succession=Yes
−
|contemporary=Whiskey Lake U
 
−
|contemporary link=intel/cores/whiskey lake u
 
 
}}
 
}}
−
'''Coffee Lake U''' ('''CFL-U''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Coffee Lake|l=arch}} microarchitecture serving as a successor to {{intel|Kaby Lake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Coffee Lake U processors are fabricated on Intel's 3rd generation enhanced [[14 nm lithography process|14nm++ process]].
+
'''Coffee Lake U''' ('''CFL-U''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Coffee Lake|l=arch}} microarchitecture serving as a successor to {{intel|Kaby Lake R|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Coffee Lake U processors are fabricated on Intel's 3rd generation enhanced [[14 nm lithography process|14nm++ process]].
 +
 
  
 
== Overview ==
 
== Overview ==
−
Coffee Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP) along with the [[eDRAM]]. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Coffee Lake U processors use {{intel|BGA-1356|Socket BGA-1528}} and incorporate 128 MiB of side cache.
+
Coffee Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP) along with the [[eDRAM]]. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Coffee LAke U processors use {{intel|BGA-1356|Socket BGA-1356}} and incorporate 64 MiB of side cache.
  
 
=== Common Features ===
 
=== Common Features ===
Line 35: Line 34:
  
 
* Dual-channel Memory
 
* Dual-channel Memory
−
** Up to DDR4-2400, LPDDR3-2133
+
** Up to DDR4-2400, LPDDR3-1866
 
** Up to 64 GiB
 
** Up to 64 GiB
−
* 16x PCIe
+
* 12x PCIe
 
* [[dual-core]]/[[quad-core]] with 2 threads per core
 
* [[dual-core]]/[[quad-core]] with 2 threads per core
 
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
 
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
Line 43: Line 42:
 
* Support [[AHCI]], [[High Definition Audio]], 4-6x [[USB 3.0]] ports, 8-10x [[USB 2.0]] ports, 2-4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
 
* Support [[AHCI]], [[High Definition Audio]], 4-6x [[USB 3.0]] ports, 8-10x [[USB 2.0]] ports, 2-4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
 
* Graphics
 
* Graphics
−
** {{intel|Iris Plus Graphics 655}} ({{intel|Gen9.5|l=arch}} GT3e)
+
** {{intel|Iris Plus Graphics 640}} ({{intel|Gen9.5|l=arch}} GT3e)
−
** 128 MiB of eDRAM side cache
 
 
** 3 independent displays supported
 
** 3 independent displays supported
−
** Base frequency of 300 MHz
+
** Base frequency of ? MHz
−
** Burst frequency of 1.05-1.2 GHz
+
** Burst frequency of ? GHz
  
 
{{clear}}
 
{{clear}}
  
 
== Coffee Lake U Processors ==
 
== Coffee Lake U Processors ==
 +
{{future information}}
 
<!-- NOTE:  
 
<!-- NOTE:  
 
           This table is generated automatically from the data in the actual articles.
 
           This table is generated automatically from the data in the actual articles.
Line 61: Line 60:
 
{{comp table start}}
 
{{comp table start}}
 
<table class="comptable sortable tc5 tc6">
 
<table class="comptable sortable tc5 tc6">
−
{{comp table header|main|18:List of Coffee Lake U Processors}}
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="21">List of Coffee Lake U Processors</th></tr>
−
{{comp table header|main|11:Main processor|3:Integrated Graphics}}
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr>
−
{{comp table header|cols|Launched|Price|Family|Cores|Threads|%L3$|%L4$|%TDP|%Frequency|%Turbo|%TV Boost|Name|%Frequency|%Turbo}}
+
{{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %TDP, Frequency, %{{intel|turbo boost|Turbo}}, Max Mem, Name, Frequency, Turbo}}
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake U]]
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake U]]
 
  |?full page name
 
  |?full page name
Line 73: Line 72:
 
  |?thread count
 
  |?thread count
 
  |?l3$ size
 
  |?l3$ size
−
|?l4$ size
 
 
  |?tdp
 
  |?tdp
 
  |?base frequency#GHz
 
  |?base frequency#GHz
Line 86: Line 84:
 
  |sort=microprocessor family, model number
 
  |sort=microprocessor family, model number
 
  |order=asc,asc
 
  |order=asc,asc
−
  |userparam=16
+
  |userparam=15
 
  |mainlabel=-
 
  |mainlabel=-
 
  |limit=100
 
  |limit=100
Line 96: Line 94:
 
== See also ==
 
== See also ==
 
{{intel coffee lake core see also}}
 
{{intel coffee lake core see also}}
 +
* {{intel|Kaby Lake|l=arch}}
 +
** {{intel|Kaby Lake R|l=core}}

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/intel/cores/coffee_lake_u"
Facts about "Coffee Lake U - Cores - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Coffee Lake U - Cores - Intel#package +
designerIntel +
first announcedApril 2, 2018 +
first launchedApril 2, 2018 +
instance ofcore +
isax86-64 +
isa familyx86 +
manufacturerIntel +
microarchitectureCoffee Lake +
nameCoffee Lake U +
packageFCBGA-1528 +
process14 nm (0.014 μm, 1.4e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +