Editing intel/cores/coffee lake s

{{intel title|Coffee Lake S|core}}
{{core
|name=Coffee Lake S
|image=coffee lake s (front).png
|caption=Package front side
|image 2=coffee lake s (back).png
|caption 2=Package back side
|developer=Intel
|manufacturer=Intel
|first announced=September 24, 2017
|first launched=October 5, 2017
|isa=x86-64
|isa family=x86
|microarch=Coffee Lake
|word=64 bit
|proc=14 nm
|tech=CMOS
|clock min=2,800 MHz
|clock max=4,000 MHz
|package module 1={{packages/intel/lga-1151}}
|predecessor=Kaby Lake S
|predecessor link=intel/cores/kaby lake s
|successor=Coffee Lake R
|successor link=intel/cores/coffee lake r
}}
'''Coffee Lake S''' ('''CFL-S''') is the name of the core for [[Intel]]'s mainstream performance line of processors based on the {{intel|Coffee Lake|l=arch}} microarchitecture serving as a successor to {{intel|Kaby Lake S|l=core}}. These chips are primarily targeted towards desktop performance to value computers, AiOs, and minis. Coffee Lake S processors are fabricated on Intel's 3rd generation enhanced [[14 nm lithography process|14nm++ process]]. Coffee Lake S is the first series of mainstream desktop PC [[hexa-core]] microprocessors from Intel.

== Overview ==
Coffee Lake S based processors are a 2-chip solution - the [[microprocessor]] and the [[chipset]]. Coffee Lake S are {{intel|LGA-1151|Socket LGA-1151}} and use {{intel|300-series}} chipset ({{intel|Platform Controller Hub|HUB}}). Despite using the same socket, those chips are not backwards-compatible with {{intel|Union Point}} (or {{intel|Sunrise Point}}). The microprocessor is connected to the chipset via 4 of the chip's 20 PCIe lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane.

=== Common Features ===
All Coffee Lake S processors have the following:

* Dual-channel Memory
** DDR4-2400-DDR4-2666
** 64 GiB
* 16x PCIe (4 of the 20 are used by the bus as described above)
* [[quad-core|4]] to [[octa core|8]] core with 4 to 16 threads (not all S models support {{intel|Hyper-Threading}})
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2)
* Graphics
** UHD Graphics ({{intel|Gen9.5|l=arch}}) {{intel|UHD Graphics 610|610}} (GT1), {{intel|UHD Graphics 630|630}} (GT2)
** Base frequency of 350 MHz
** Burst frequency of 1-1.15 GHz
{{clear}}

== Coffee Lake S Processors ==
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{{comp table start}}
<table class="comptable sortable tc5 tc6">
{{comp table header|main|13:List of Coffee Lake S-based Processors}}
{{comp table header|main|10:Main processor|3:GPU}}
{{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %TDP, %Frequency, Turbo, Max Mem, Name, Frequency, Turbo}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake S]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core count
 |?thread count
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=15
 |mainlabel=-
 |limit=100
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake S]]}}
</table>
{{comp table end}}

== See also ==
[[File:coffee lake s.png|right|400px]]
{{intel coffee lake core see also}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Coffee Lake S - Cores - Intel#package +
designer	Intel +
first announced	September 24, 2017 +
first launched	October 5, 2017 +
instance of	core +
isa	x86-64 +
isa family	x86 +
main image	+ and +
main image caption	Package front side + and Package back side +
manufacturer	Intel +
microarchitecture	Coffee Lake +
name	Coffee Lake S +
package	FCLGA-1151 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	LGA-1151 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +