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Latest revision | Your text | ||
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|clock min=2,300 MHz | |clock min=2,300 MHz | ||
|clock max=2,900 MHz | |clock max=2,900 MHz | ||
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|predecessor=Kaby Lake H | |predecessor=Kaby Lake H | ||
|predecessor link=intel/cores/kaby lake h | |predecessor link=intel/cores/kaby lake h | ||
− | |successor= | + | |successor=Ice Lake H |
− | |successor link=intel/cores/ | + | |successor link=intel/cores/ice lake h |
|succession=Yes | |succession=Yes | ||
}} | }} | ||
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** Up to DDR4-2666, LPDDR3-2133 | ** Up to DDR4-2666, LPDDR3-2133 | ||
* 16x PCIe (4 of the 20 are used by the bus as described above) | * 16x PCIe (4 of the 20 are used by the bus as described above) | ||
− | * [[ | + | * [[dual-core|2]] to [[quad-core|4]] core with 2 threads per core |
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, AVX2) | * Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, AVX2) | ||
* Graphics | * Graphics | ||
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{{comp table header|main|10:Main processor|3:Integrated Graphics|6:Features}} | {{comp table header|main|10:Main processor|3:Integrated Graphics|6:Features}} | ||
{{comp table header|cols|Launched|Price|Family|Cores|Threads|L3$|%TDP|%Frequency|%Turbo|%TV Boost|Name|%Frequency|%Turbo|ECC|vPro|TSX|TXT|SIPP}} | {{comp table header|cols|Launched|Price|Family|Cores|Threads|L3$|%TDP|%Frequency|%Turbo|%TV Boost|Name|%Frequency|%Turbo|ECC|vPro|TSX|TXT|SIPP}} | ||
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake H | + | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake H]] |
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|?full page name | |?full page name | ||
|?model number | |?model number | ||
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== See also == | == See also == | ||
{{intel coffee lake core see also}} | {{intel coffee lake core see also}} | ||
+ | * {{intel|Kaby Lake|l=arch}} | ||
+ | ** {{intel|Kaby Lake H|l=core}} |
Facts about "Coffee Lake H - Cores - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Coffee Lake H - Cores - Intel#package + |
designer | Intel + |
first announced | April 2, 2018 + |
first launched | April 2, 2018 + |
instance of | core + |
isa | x86-64 + |
main image | + |
manufacturer | Intel + |
microarchitecture | Coffee Lake + |
name | Coffee Lake H + |
package | FCBGA-1440 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |