From WikiChip
Editing intel/cores/coffee lake h

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 14: Line 14:
 
|clock min=2,300 MHz
 
|clock min=2,300 MHz
 
|clock max=2,900 MHz
 
|clock max=2,900 MHz
|package module 1={{packages/intel/fcbga-1440}}
 
 
|predecessor=Kaby Lake H
 
|predecessor=Kaby Lake H
 
|predecessor link=intel/cores/kaby lake h
 
|predecessor link=intel/cores/kaby lake h
|successor=Coffee Lake HR
+
|successor=Cannonlake H
|successor link=intel/cores/coffee lake hr
+
|successor link=intel/cores/cannonlake h
 
|succession=Yes
 
|succession=Yes
 
}}
 
}}
Line 35: Line 34:
 
** Up to DDR4-2666, LPDDR3-2133
 
** Up to DDR4-2666, LPDDR3-2133
 
* 16x PCIe (4 of the 20 are used by the bus as described above)
 
* 16x PCIe (4 of the 20 are used by the bus as described above)
* [[quad-core|4]] to [[hexa-core|6]] core with 2 threads per core (not all models have {{intel|Hyper-Threading}})
+
* [[dual-core|2]] to [[quad-core|4]] core with 2 threads per core
 
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, AVX2)
 
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, AVX2)
 
* Graphics
 
* Graphics
Line 57: Line 56:
 
{{comp table header|main|10:Main processor|3:Integrated Graphics|6:Features}}
 
{{comp table header|main|10:Main processor|3:Integrated Graphics|6:Features}}
 
{{comp table header|cols|Launched|Price|Family|Cores|Threads|L3$|%TDP|%Frequency|%Turbo|%TV Boost|Name|%Frequency|%Turbo|ECC|vPro|TSX|TXT|SIPP}}
 
{{comp table header|cols|Launched|Price|Family|Cores|Threads|L3$|%TDP|%Frequency|%Turbo|%TV Boost|Name|%Frequency|%Turbo|ECC|vPro|TSX|TXT|SIPP}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake H]] [[tdp::<64W]]
+
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake H]]
|?full page name
 
|?model number
 
|?first launched
 
|?release price
 
|?microprocessor family
 
|?core count
 
|?thread count
 
|?l3$ size
 
|?tdp
 
|?base frequency#GHz
 
|?turbo frequency (1 core)#GHz
 
|?intel thermal velocity boost#GHz
 
|?integrated gpu
 
|?integrated gpu base frequency
 
|?integrated gpu max frequency
 
|?has ecc memory support
 
|?has intel vpro technology
 
|?has transactional synchronization extensions
 
|?has intel trusted execution technology
 
|?has intel stable image platform program support
 
|format=template
 
|template=proc table 3
 
|userparam=20:16
 
|mainlabel=-
 
}}
 
{{comp table header|lsep|20:High-power models}}
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake H]] [[tdp::>65W]]
 
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
Line 116: Line 88:
 
== See also ==
 
== See also ==
 
{{intel coffee lake core see also}}
 
{{intel coffee lake core see also}}
 +
* {{intel|Kaby Lake|l=arch}}
 +
** {{intel|Kaby Lake H|l=core}}

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Coffee Lake H - Cores - Intel#package +
designerIntel +
first announcedApril 2, 2018 +
first launchedApril 2, 2018 +
instance ofcore +
isax86-64 +
main imageFile:coffee lake h (front).png +
manufacturerIntel +
microarchitectureCoffee Lake +
nameCoffee Lake H +
packageFCBGA-1440 +
process14 nm (0.014 μm, 1.4e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +