From WikiChip
Editing intel/cores/cascade lake sp
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 20: | Line 20: | ||
|successor=Ice Lake SP | |successor=Ice Lake SP | ||
|successor link=intel/cores/ice lake sp | |successor link=intel/cores/ice lake sp | ||
− | |||
− | |||
}} | }} | ||
'''Cascade Lake SP''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as the successor to {{intel|Skylake SP|l=core}}. These chips support up to 8-way multiprocessing, up to [[28 cores]], incorporate a new {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake SP-based chips are manufactured on an enhanced [[14 nm process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. | '''Cascade Lake SP''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as the successor to {{intel|Skylake SP|l=core}}. These chips support up to 8-way multiprocessing, up to [[28 cores]], incorporate a new {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake SP-based chips are manufactured on an enhanced [[14 nm process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. |
Facts about "Cascade Lake SP - Cores - Intel"
chipset | Lewisburg + |
designer | Intel + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | ![]() |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake SP + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket P + and LGA-3647 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |