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| | {{intel title|Cascade Lake R|core}} | | {{intel title|Cascade Lake R|core}} |
| | {{core | | {{core |
| − | |name=Cascade Lake R | + | |name=Cascade Lake SP |
| | |image=cascade lake sp (front).png | | |image=cascade lake sp (front).png |
| | |developer=Intel | | |developer=Intel |
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| | |tech=CMOS | | |tech=CMOS |
| | |package name 1=intel,fclga_3647 | | |package name 1=intel,fclga_3647 |
| − | |predecessor=Skylake SP | + | |predecessor=Cascade Lake SP |
| − | |predecessor link=intel/cores/skylake sp | + | |predecessor link=intel/cores/cascade lake sp |
| | |successor=Ice Lake SP | | |successor=Ice Lake SP |
| | |successor link=intel/cores/ice lake sp | | |successor link=intel/cores/ice lake sp |
| − | |contemporary=Cascade Lake SP
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| − | |contemporary link=intel/cores/cascade lake sp
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| | }} | | }} |
| | '''Cascade Lake R''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance Refresh''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as mid-cycle refresh to {{intel|Cascade Lake SP|l=core}}. Cascade Lake R only targets mainstream entry and mid-range servers and therefore only support up to 2-way multiprocessing. As with {{\\|Cascade Lake SP}}, these chips also support up to [[28 cores]], incorporate {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake R-based chips are manufactured on an enhanced [[14 nm process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. | | '''Cascade Lake R''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance Refresh''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as mid-cycle refresh to {{intel|Cascade Lake SP|l=core}}. Cascade Lake R only targets mainstream entry and mid-range servers and therefore only support up to 2-way multiprocessing. As with {{\\|Cascade Lake SP}}, these chips also support up to [[28 cores]], incorporate {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake R-based chips are manufactured on an enhanced [[14 nm process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. |
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| | Cascade Lake R-based models are branded as the 2nd-generation {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, and {{intel|Xeon Gold}} [[processor families]]. | | Cascade Lake R-based models are branded as the 2nd-generation {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, and {{intel|Xeon Gold}} [[processor families]]. |
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| − | == Overview ==
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| − | Cascade Lake R processors are based on Intel's {{intel|Cascade Lake|l=arch}} microarchitecture intended to enhance the original {{\\|Cascade Lake SP}} lineup. These processors introduce a significant price cut compared to original SKUs or additional cores and the higher frequency at comparable price. The intended purpose of this release is to elevate the performance-per-dollar for entry-level and mid-range server processors.
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| − | As with {{\\|Skylake SP}}, Cascade Lake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|cascade lake#Scalability|Cascade Lake § Scalability|l=arch}}).
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| − | === Common Features ===
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| − | All Cascade Lake R processors have the following:
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| − | * Hexa-channel memory
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| − | ** 1 TiB, 2 TiB medium memory support variants (''M'' suffix), and 4.5 TiB for extended memory variants (''L'' suffix)
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| − | ** UP to DDR4-2933 MT/s
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| − | ** [[ECC]] support
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| − | * '''TDP:''' 85 W to 205 W
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| − | * '''PCIe:''' x48 Lanes of PCIe Gen 3
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| − | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL, AVX512VNNI)
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| − | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
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| − | ** Silver and up also have {{intel|Hyper-Threading}} and {{intel|Turbo Boost}}
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| − | ** Gold and up also have Node Controller Support and offer Integrated Omni-Path Fabric Interface options
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| − | {{clear}}
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| − |
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| − | === Naming Scheme ===
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| − | Cascade Lake SKUs follow the following naming scheme.
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| − |
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| − | :[[File:cascade lake naming scheme.svg|600px]]
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| − | Where,
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| − | * "''F''" suffix integrates the {{intel|Omni-Path}} Host Fabric Interface (HFI) die on-package
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| − | * "''L''" suffix indicates the SKU is a large memory (4.5 TiB) tier SKU
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| − | * "''M''" suffix indicates the SKU is a medium memory (2 TiB) tier SKU
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| − | * "''N''" suffix indicates the SKU is a networking-specialized model
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| − | * "''S''" suffix indicates the SKU is a search application-specialized model
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| − | * "''T''" suffix indicates that SKU has an extended lifetime (10 year use) guarantees and [[NEBS]]-friendly packing specification
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| − | * "''V''" suffix indicates the SKU targets the VM density value market
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| − | * "''Y''" suffix indicates the SKU has {{intel|Speed Select Technology}} (SST)
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| − | * "''U''" suffix indicates the SKU is a single-socket model (even if part of the [[Xeon Gold]] family that normally supports up two 4-way [[SMP]])
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| − | * "''R''" suffix indicates the SKU is a dual-socket model (even if part of the [[Xeon Gold]] family that normally supports up two 4-way [[SMP]])
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| − |
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| − | == Cascade Lake R Processors ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc5 tc6 tc14">
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| − | {{comp table header|main|12:List of Cascade Lake R-based Processors}}
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| − | {{comp table header|main|8:Main Processor|1:Cache|2:Memory}}
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| − | {{comp table header|cols|Family|Price|Launched|Cores|Threads|Frequency|Max Turbo|%TDP|L3$|Mem Type|Max Mem}}
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| − | {{comp table header|lsep|25:[[Multiprocessors]] (2-way)}}
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| − | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake R]] [[max cpu count::2]]
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| − | |?full page name
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| − | |?model number
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| − | |?microprocessor family
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| − | |?release price
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| − | |?first launched
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| − | |?core count
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| − | |?thread count
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| − | |?base frequency#GHz
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| − | |?turbo frequency (1 core)#GHz
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| − | |?tdp
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| − | |?l3$ size
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| − | |?supported memory type
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| − | |?max memory#TiB
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=13
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| − | |mainlabel=-
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| − | |limit=75
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| − | |valuesep=,
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| − | |sort=model number
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake R]]}}
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| − | </table>
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| − | {{comp table end}}
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| − |
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| − | === SKU Comparison ===
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| − | Below are a number of SKU comparison graphs based on their specifications.
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| − |
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| − | <div style="float: left; margin: 10px">
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| − | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake R]]
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| − | |?core count
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| − | |?base frequency
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| − | |charttitle=Cores vs. Base Frequency
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| − | |numbersaxislabel=Frequency (MHz)
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| − | |labelaxislabel=Core Count
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| − | |height=400
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| − | |width=400
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| − | |theme=vector
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| − | |group=property
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| − | |grouplabel=subject
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| − | |charttype=scatter
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| − | |format=jqplotseries
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| − | |mainlabel=-
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| − | }}
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| − | </div>
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| − |
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| − | <div style="float: left; margin: 10px">
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| − | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake R]]
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| − | |?core count
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| − | |?turbo frequency (1 core)
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| − | |charttitle=Cores vs. Turbo Frequency
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| − | |numbersaxislabel=Frequency (MHz)
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| − | |labelaxislabel=Core Count
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| − | |height=400
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| − | |width=400
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| − | |theme=vector
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| − | |group=property
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| − | |grouplabel=subject
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| − | |charttype=scatter
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| − | |format=jqplotseries
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| − | |mainlabel=-
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| − | }}
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| − | </div>
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| − |
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| − | <div style="float: left; margin: 10px">
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| − | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake R]]
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| − | |?core count
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| − | |?tdp
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| − | |charttitle=Cores vs. TDP
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| − | |numbersaxislabel=TDP (W)
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| − | |labelaxislabel=Core Count
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| − | |height=400
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| − | |width=400
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| − | |theme=vector
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| − | |group=property
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| − | |grouplabel=subject
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| − | |charttype=scatter
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| − | |format=jqplotseries
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| − | |mainlabel=-
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| − | }}
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| − | </div>
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| − |
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| − | <div style="float: left; margin: 10px">
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| − | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake R]]
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| − | |?turbo frequency (1 core)
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| − | |?tdp
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| − | |charttitle=Frequency vs. TDP
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| − | |numbersaxislabel=TDP (W)
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| − | |labelaxislabel=Frequency (MHz)
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| − | |height=400
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| − | |width=400
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| − | |theme=vector
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| − | |group=property
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| − | |grouplabel=subject
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| − | |charttype=scatter
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| − | |format=jqplotseries
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| − | |mainlabel=-
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| − | }}
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| − | </div>
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| − |
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| − | {{clear}}
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| − |
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| − | == See also ==
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| − | {{intel cascade lake core see also}}
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