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== Overview == | == Overview == | ||
Cascade Lake AP comprise of two {{intel|Cascade Lake|l=arch}} dies packaged together a single BGA-5903 substrate. Those processors support up to 56 cores, 112 threads, and up to 12 DDR4 channels. | Cascade Lake AP comprise of two {{intel|Cascade Lake|l=arch}} dies packaged together a single BGA-5903 substrate. Those processors support up to 56 cores, 112 threads, and up to 12 DDR4 channels. | ||
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=== Common Features === | === Common Features === | ||
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** ECC support | ** ECC support | ||
* '''TDP:''' 250 W to 400 W | * '''TDP:''' 250 W to 400 W | ||
− | * '''PCIe:''' x40 Lanes of PCIe Gen 3 | + | * '''PCIe:''' x40 Lanes of PCIe Gen 3 |
* '''ISA:''' Everything up to {{x86|AVX-512}} (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, {{x86|AVX512DQ}}, {{x86|AVX512VL}}, {{x86|AVX512VNNI}}) | * '''ISA:''' Everything up to {{x86|AVX-512}} (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, {{x86|AVX512DQ}}, {{x86|AVX512VL}}, {{x86|AVX512VNNI}}) | ||
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}} | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}} | ||
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|?core count | |?core count | ||
|?base frequency | |?base frequency | ||
− | |charttitle=Cores vs. | + | |charttitle=Cores vs. Frequency |
|numbersaxislabel=Frequency (MHz) | |numbersaxislabel=Frequency (MHz) | ||
|labelaxislabel=Core Count | |labelaxislabel=Core Count | ||
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{{clear}} | {{clear}} | ||
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== See also == | == See also == | ||
{{intel cascade lake core see also}} | {{intel cascade lake core see also}} |
Facts about "Cascade Lake AP - Cores - Intel"
designer | Intel + |
instance of | core + |
isa | x86-64 + |
main image | + |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake AP + |
package | FCBGA-5903 + |
platform | Walker Pass + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |