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{{core | {{core | ||
|name=Cascade Lake AP | |name=Cascade Lake AP | ||
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|developer=Intel | |developer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
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'''Cascade Lake AP''' ('''CLX-AP''', '''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture part of the {{intel|Walker Pass|l=platform}} platform. | '''Cascade Lake AP''' ('''CLX-AP''', '''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture part of the {{intel|Walker Pass|l=platform}} platform. | ||
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+ | {{future information}} | ||
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== Overview == | == Overview == | ||
− | Cascade Lake AP comprise of | + | Cascade Lake AP comprise of multiple {{intel|Cascade Lake|l=arch}} dies in a single BGA-5903 package. Those processors support up to 48 cores, 96 threads, and up to 12 DDR4 channels. |
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=== Common Features === | === Common Features === | ||
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** ECC support | ** ECC support | ||
* '''TDP:''' 250 W to 400 W | * '''TDP:''' 250 W to 400 W | ||
− | * '''PCIe:''' | + | * '''PCIe:''' x80 Lanes of PCIe Gen 3 |
* '''ISA:''' Everything up to {{x86|AVX-512}} (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, {{x86|AVX512DQ}}, {{x86|AVX512VL}}, {{x86|AVX512VNNI}}) | * '''ISA:''' Everything up to {{x86|AVX-512}} (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, {{x86|AVX512DQ}}, {{x86|AVX512VL}}, {{x86|AVX512VNNI}}) | ||
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}} | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}} | ||
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{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc4 tc5 tc11"> |
{{comp table header|main|11:List of Cascade Lake AP-based Processors}} | {{comp table header|main|11:List of Cascade Lake AP-based Processors}} | ||
− | {{comp table header|cols|Launched|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo}} | + | {{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo}} |
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]] | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
|?first launched | |?first launched | ||
+ | |?release price | ||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
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|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=11 |
|sort=model number | |sort=model number | ||
|mainlabel=- | |mainlabel=- | ||
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{{comp table end}} | {{comp table end}} | ||
− | == | + | == Cascade Lake AP Processors == |
− | + | {{empty section}} | |
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== See also == | == See also == | ||
{{intel cascade lake core see also}} | {{intel cascade lake core see also}} |
Facts about "Cascade Lake AP - Cores - Intel"
designer | Intel + |
instance of | core + |
isa | x86-64 + |
main image | + |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake AP + |
package | FCBGA-5903 + |
platform | Walker Pass + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |