From WikiChip
Editing intel/cores/cascade lake ap
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 2: | Line 2: | ||
{{core | {{core | ||
|name=Cascade Lake AP | |name=Cascade Lake AP | ||
− | |image= | + | |no image=Yes |
|developer=Intel | |developer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|isa=x86-64 | |isa=x86-64 | ||
|microarch=Cascade Lake | |microarch=Cascade Lake | ||
− | |||
|word=64 bit | |word=64 bit | ||
|proc=14 nm | |proc=14 nm | ||
Line 13: | Line 12: | ||
|package name 1=intel,fcbga_5903 | |package name 1=intel,fcbga_5903 | ||
}} | }} | ||
− | '''Cascade Lake AP''' ( | + | '''Cascade Lake AP''' ('''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture part of the {{intel|Walker Pass|l=platform}}. |
+ | |||
+ | |||
+ | {{future information}} | ||
− | |||
== Overview == | == Overview == | ||
− | Cascade Lake AP comprise of | + | Cascade Lake AP comprise of multiple {{intel|Cascade Lake|l=arch}} dies in a single package. Those processors support up to 48 cores, 96 threads, and up to 12 DDR4 channels. |
− | |||
− | |||
=== Common Features === | === Common Features === | ||
* 12-channel memory | * 12-channel memory | ||
− | ** UP to DDR4- | + | ** UP to DDR4-2666 MT/s |
** ECC support | ** ECC support | ||
− | * '''TDP:''' | + | * '''TDP:''' ? W to ? W |
− | * '''PCIe:''' | + | * '''PCIe:''' x? Lanes of PCIe Gen 3 |
− | * '''ISA:''' Everything up to | + | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL, AVX512VNNI) |
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}} | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}} | ||
{{clear}} | {{clear}} | ||
− | == Cascade Lake AP Processors== | + | == Cascade Lake AP Processors == |
− | + | {{empty section}} | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | {{ | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== See also == | == See also == | ||
{{intel cascade lake core see also}} | {{intel cascade lake core see also}} |
Facts about "Cascade Lake AP - Cores - Intel"
designer | Intel + |
instance of | core + |
isa | x86-64 + |
main image | + |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake AP + |
package | FCBGA-5903 + |
platform | Walker Pass + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |