From WikiChip
Editing intel/core x
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 35: | Line 35: | ||
=== Skylake === | === Skylake === | ||
{{see also|intel/microarchitectures/skylake|intel/cores/skylake_x|l1=Skylake µarch|l2=Skylake X core}} | {{see also|intel/microarchitectures/skylake|intel/cores/skylake_x|l1=Skylake µarch|l2=Skylake X core}} | ||
− | Skylake-based Core X processors were introduced at Computex 2017. Those processors incorporate a large number of changes over their {{intel|Broadwell|l=arch}} counterparts which brings along a performance increase in addition to other improvements. Those processors are also the first to incorporate the new {{x86|AVX-512}} extension. | + | Skylake-based Core X processors were introduced at Computex 2017. Those processors incorporate a large number of changes over their {{intel|Broadwell|l=arch}} counterparts which brings along a performance increase in addition to other improvements. Those processors are also the first to incorporate the new {{x86|AVX-512}} extension. |
− | * '''TDP:''' 140, | + | * '''TDP:''' 140, 160 W |
− | |||
− | |||
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, and AVX-512) | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, and AVX-512) | ||
− | * '''Tech:''' {{intel|Turbo Boost|Turbo Boost 2.0}}, {{intel|Turbo Max|Turbo Max 3.0}}, {{intel|VT-x}}, {{intel|VT-d}}, and {{intel| | + | * '''Tech:''' {{intel|Turbo Boost|Turbo Boost 2.0}}, {{intel|Turbo Max|Turbo Max 3.0}}, {{intel|Hyper-Threading}}, {{intel|VT-x}}, {{intel|VT-d}}, {{intel|SpeedStep}}, Software Guard ({{intel|SGX}}), and Memory Protection ({{intel|MPX}}) |
<!-- NOTE: | <!-- NOTE: | ||
Line 51: | Line 49: | ||
--> | --> | ||
{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc14 tc15"> |
<tr class="comptable-header"><th> </th><th colspan="19">List of Skylake-based Core X Processors</th></tr> | <tr class="comptable-header"><th> </th><th colspan="19">List of Skylake-based Core X Processors</th></tr> | ||
− | <tr class="comptable-header"><th> </th><th colspan="10">Main processor</th><th>Memory</th><th>I/O</th><th>Features</th></tr> | + | <tr class="comptable-header"><th> </th><th colspan="10">Main processor</th><th colspan="2">Memory</th><th>I/O</th><th>Features</th></tr> |
− | {{comp table header 1|cols=Price, Launched, Cores, Threads, L2$, L3$ | + | {{comp table header 1|cols=Price, Process, Launched, Cores, Threads, L2$, L3$, Frequency, Turbo, TDP, Max Mem, Memory Type, Max [[PCIe]], Turbo Max}} |
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake X]] [[microarchitecture::Skylake | + | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake X]] [[microarchitecture::Skylake]] |
|?full page name | |?full page name | ||
|?model number | |?model number | ||
|?release price | |?release price | ||
+ | |?process | ||
|?first launched | |?first launched | ||
|?core count | |?core count | ||
Line 64: | Line 63: | ||
|?l2$ size | |?l2$ size | ||
|?l3$ size | |?l3$ size | ||
− | |||
|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
− | |? | + | |?tdp |
+ | |?max memory#GiB | ||
|?supported memory type | |?supported memory type | ||
− | |? | + | |?max pcie lanes |
|?has intel turbo boost max technology 3 0 | |?has intel turbo boost max technology 3 0 | ||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=16:16 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake X]] [[microarchitecture::Skylake | + | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake X]] [[microarchitecture::Skylake]]}} |
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
Line 85: | Line 84: | ||
* '''TDP:''' 112 W | * '''TDP:''' 112 W | ||
− | |||
− | |||
* '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2) | * '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2) | ||
− | * '''Tech:''' {{intel|Turbo Boost|Turbo Boost 2.0}}, {{intel|Turbo Max|Turbo Max 3.0}}, {{intel|VT-x}}, {{intel|VT-d}}, and {{intel| | + | * '''Tech:''' {{intel|Turbo Boost|Turbo Boost 2.0}}, {{intel|Turbo Max|Turbo Max 3.0}}, {{intel|VT-x}}, {{intel|VT-d}}, {{intel|SpeedStep}}, Software Guard ({{intel|SGX}}), and Memory Protection ({{intel|MPX}}) |
+ | * 16x PCIe lanes | ||
+ | * Up to 64 [[GiB]] of dual-channel DDR-2666 memory | ||
<!-- NOTE: | <!-- NOTE: | ||
Line 98: | Line 97: | ||
--> | --> | ||
{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc12"> |
<tr class="comptable-header"><th> </th><th colspan="19">List of Kaby Lake-based Core X Processors</th></tr> | <tr class="comptable-header"><th> </th><th colspan="19">List of Kaby Lake-based Core X Processors</th></tr> | ||
− | <tr class="comptable-header"><th> </th><th colspan=" | + | <tr class="comptable-header"><th> </th><th colspan="10">Main processor</th><th colspan="9">Features</th></tr> |
− | {{comp table header 1|cols=Price, Launched, Cores, Threads, L2$, L3$, Frequency, Turbo, TDP, {{intel|Hyper-Threading|HT}}}} | + | {{comp table header 1|cols=Price, Process, Launched, Cores, Threads, L2$, L3$, Frequency, Turbo, TDP, {{intel|Hyper-Threading|HT}}}} |
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake X]] [[microarchitecture::Kaby Lake]] | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake X]] [[microarchitecture::Kaby Lake]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
|?release price | |?release price | ||
+ | |?process | ||
|?first launched | |?first launched | ||
|?core count | |?core count | ||
Line 117: | Line 117: | ||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=13:13 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake X]] [[microarchitecture::Kaby Lake]]}} | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake X]] [[microarchitecture::Kaby Lake]]}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} |
Facts about "Core X - Intel"
designer | Intel + |
first announced | May 30, 2017 + |
full page name | intel/core x + |
instance of | microprocessor family + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Skylake + and Kaby Lake + |
name | Core X + |
package | FCLGA-2066 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket R + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |