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=== Skylake === | === Skylake === | ||
{{see also|intel/microarchitectures/skylake|intel/cores/skylake_x|l1=Skylake µarch|l2=Skylake X core}} | {{see also|intel/microarchitectures/skylake|intel/cores/skylake_x|l1=Skylake µarch|l2=Skylake X core}} | ||
− | Skylake-based Core X processors were introduced at Computex 2017. Those processors incorporate a large number of changes over their {{intel|Broadwell|l=arch}} counterparts which brings along a performance increase in addition to other improvements. Those processors are also the first to incorporate the new {{x86|AVX-512}} extension. | + | Skylake-based Core X processors were introduced at Computex 2017. Those processors incorporate a large number of changes over their {{intel|Broadwell|l=arch}} counterparts which brings along a performance increase in addition to other improvements. Those processors are also the first to incorporate the new {{x86|AVX-512}} extension. |
− | * '''TDP:''' 140 | + | * '''TDP:''' 140 W |
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* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, and AVX-512) | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, and AVX-512) | ||
− | * '''Tech:''' {{intel|Turbo Boost|Turbo Boost 2.0}}, {{intel|Turbo Max|Turbo Max 3.0}}, {{intel|VT-x}}, {{intel|VT-d}}, and {{intel| | + | * '''Tech:''' {{intel|Turbo Boost|Turbo Boost 2.0}}, {{intel|Turbo Max|Turbo Max 3.0}}, {{intel|Hyper-Threading}}, {{intel|VT-x}}, {{intel|VT-d}}, {{intel|SpeedStep}}, Software Guard ({{intel|SGX}}), and Memory Protection ({{intel|MPX}}) |
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{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable"> |
<tr class="comptable-header"><th> </th><th colspan="19">List of Skylake-based Core X Processors</th></tr> | <tr class="comptable-header"><th> </th><th colspan="19">List of Skylake-based Core X Processors</th></tr> | ||
− | <tr class="comptable-header"><th> </th><th colspan=" | + | <tr class="comptable-header"><th> </th><th colspan="8">Main processor</th><th colspan="2">Memory</th><th colspan="2">I/O</th></tr> |
− | {{comp table header 1|cols=Price, Launched, Cores, Threads, | + | {{comp table header 1|cols=Price, Process, Launched, Cores, Threads, Frequency, Turbo, TDP, Max Mem, Memory Type, Max [[PCIe]]}} |
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[ | + | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Core X]] [[microarchitecture::Skylake]] |
|?full page name | |?full page name | ||
|?model number | |?model number | ||
|?release price | |?release price | ||
+ | |?process | ||
|?first launched | |?first launched | ||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
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|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
− | |? | + | |?tdp |
+ | |?max memory#GiB | ||
|?supported memory type | |?supported memory type | ||
− | |? | + | |?max pcie lanes |
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|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=13 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[ | + | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Core X]] [[microarchitecture::Skylake]]}} |
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
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=== Kaby Lake === | === Kaby Lake === | ||
{{see also|intel/microarchitectures/kaby lake|intel/cores/kaby lake x|l1=Kaby Lake µarch|l2=Kaby Lake X core}} | {{see also|intel/microarchitectures/kaby lake|intel/cores/kaby lake x|l1=Kaby Lake µarch|l2=Kaby Lake X core}} | ||
− | Kaby Lake-based Core X processors were introduced at Computex 2017 at the same time as the Skylake models. Despite that, those processors are far more similar to the high-end {{intel|Core i7}} ({{intel|Kaby Lake S|l=core}} core) contemporaries in terms of features and capabilities vs the Skylake Core X variants. Likewise, they do not incorporate some of the more significant features such as a high core count, the cache | + | Kaby Lake-based Core X processors were introduced at Computex 2017 at the same time as the Skylake models. Despite that, those processors are far more similar to the high-end {{intel|Core i7}} ({{intel|Kaby Lake S|l=core}} core) contemporaries in terms of features and capabilities vs the Skylake Core X variants. Likewise, they do not incorporate some of the more significant features such as a high core count, the new cache system, and {{x86|AVX-512}}. |
* '''TDP:''' 112 W | * '''TDP:''' 112 W | ||
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* '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2) | * '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2) | ||
− | * '''Tech:''' {{intel|Turbo Boost|Turbo Boost 2.0}}, {{intel|Turbo Max|Turbo Max 3.0}}, {{intel|VT-x}}, {{intel|VT-d}}, and {{intel| | + | * '''Tech:''' {{intel|Turbo Boost|Turbo Boost 2.0}}, {{intel|Turbo Max|Turbo Max 3.0}}, {{intel|VT-x}}, {{intel|VT-d}}, {{intel|SpeedStep}}, Software Guard ({{intel|SGX}}), and Memory Protection ({{intel|MPX}}) |
+ | * 16x PCIe lanes | ||
+ | * Up to 64 [[GiB]] of dual-channel DDR-2666 memory | ||
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{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc10"> |
<tr class="comptable-header"><th> </th><th colspan="19">List of Kaby Lake-based Core X Processors</th></tr> | <tr class="comptable-header"><th> </th><th colspan="19">List of Kaby Lake-based Core X Processors</th></tr> | ||
− | <tr class="comptable-header"><th> </th><th colspan=" | + | <tr class="comptable-header"><th> </th><th colspan="8">Main processor</th><th colspan="9">Features</th></tr> |
− | {{comp table header 1|cols=Price, Launched, Cores, Threads | + | {{comp table header 1|cols=Price, Process, Launched, Cores, Threads, Frequency, Turbo, TDP, {{intel|Hyper-Threading|HT}}}} |
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[ | + | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Core X]] [[microarchitecture::Kaby Lake]] |
|?full page name | |?full page name | ||
|?model number | |?model number | ||
|?release price | |?release price | ||
+ | |?process | ||
|?first launched | |?first launched | ||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
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|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
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|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[ | + | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Core X]] [[microarchitecture::Kaby Lake]]}} |
</table> | </table> | ||
{{comp table end}} | {{comp table end}} |
Facts about "Core X - Intel"
designer | Intel + |
first announced | May 30, 2017 + |
full page name | intel/core x + |
instance of | microprocessor family + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Skylake + and Kaby Lake + |
name | Core X + |
package | FCLGA-2066 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket R + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |