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=== Skylake Refresh === | === Skylake Refresh === | ||
{{see also|intel/cores/skylake x refresh|l1=Skylake X Refresh}} | {{see also|intel/cores/skylake x refresh|l1=Skylake X Refresh}} | ||
− | In late 2018 Intel {{intel|Skylake X Refresh|l=core|refreshed}} the entire {{intel|Skylake X|l=core}} lineup. In addition to the higher clock frequencies achieved as a result of utilizing their mature [[14 nm process]], those processors also | + | In late 2018 Intel {{intel|Skylake X Refresh|l=core|refreshed}} the entire {{intel|Skylake X|l=core}} lineup. In addition to the higher clock frequencies achieved as a result of utilizing their mature [[14 nm process]], those processors also utilize a [[solder thermal interface material]] instead of a paste, increasing the thermal conductivity and improving the avilable [[overclocking]] headroom. The refreshed lineup got rid of the [[hexa-core]] part and eliminates the PCIe lanes-based segmentation, providing x44 PCIe lanes on all models. Additionally, all models under [[12 cores]] come with a larger [[L3 cache]]. Most of the low All models have the following common features: |
* '''TDP:''' 165 W | * '''TDP:''' 165 W |
Facts about "Core X - Intel"
designer | Intel + |
first announced | May 30, 2017 + |
full page name | intel/core x + |
instance of | microprocessor family + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Skylake + and Kaby Lake + |
name | Core X + |
package | FCLGA-2066 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket R + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |