From WikiChip
Editing intel/core i5
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 579: | Line 579: | ||
* '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2) | * '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2) | ||
* '''Tech:''' {{intel|SpeedStep}}, {{intel|Speed Shift}}, {{intel|Turbo Boost}} 2.0, {{intel|VT-x}}, {{intel|VT-d}}/{{intel|EPT}}, {{intel|TSX}}, {{intel|Flex Memory}}, {{intel|Smart Response}}, {{intel|My WiFi}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|Secure Key}} | * '''Tech:''' {{intel|SpeedStep}}, {{intel|Speed Shift}}, {{intel|Turbo Boost}} 2.0, {{intel|VT-x}}, {{intel|VT-d}}/{{intel|EPT}}, {{intel|TSX}}, {{intel|Flex Memory}}, {{intel|Smart Response}}, {{intel|My WiFi}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|Secure Key}} | ||
+ | |||
+ | Vão todos tomar no cu | ||
== 9th generation (Coffee Lake Refresh) == | == 9th generation (Coffee Lake Refresh) == |
Facts about "Core i5 - Intel"
designer | Intel + |
first announced | June 17, 2009 + |
first launched | September 2009 + |
full page name | intel/core i5 + |
instance of | microprocessor family + |
instruction set architecture | IA-32 + and x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Nehalem +, Westmere +, Sandy Bridge +, Ivy Bridge +, Haswell +, Broadwell +, Skylake +, Kaby Lake +, Coffee Lake + and Ice Lake + |
name | Intel Core i5 + |
package | FCBGA-1440 +, FCBGA-1364 +, FCBGA-1288 +, FCBGA-1168 +, FCLGA-1155 +, FCLGA-1151 +, FCLGA-1150 +, FCBGA-1023 +, FCPGA-988 + and FCPGA-946 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-1151 +, LGA-1150 +, LGA-1155 +, LGA-1156 +, Socket G1 +, Socket G2 + and Socket G3 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |