From WikiChip
Editing intel/core i5/i5-9500
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
{{intel title|Core i5-9500}} | {{intel title|Core i5-9500}} | ||
− | {{ | + | {{mpu |
+ | |future=Yes | ||
|name=Core i5-9500 | |name=Core i5-9500 | ||
− | |image= | + | |no image=Yes |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=i5-9500 | |model number=i5-9500 | ||
− | |||
− | |||
|market=Desktop | |market=Desktop | ||
− | |||
− | |||
− | |||
− | |||
|family=Core i5 | |family=Core i5 | ||
|series=i5-9000 | |series=i5-9000 | ||
|locked=Yes | |locked=Yes | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch= | + | |microarch=Ice Lake |
− | + | |core name=Ice Lake S | |
− | + | |process=10 nm | |
− | |core name= | ||
− | |||
− | |||
− | |||
− | |process= | ||
|technology=CMOS | |technology=CMOS | ||
− | |||
|word size=64 bit | |word size=64 bit | ||
− | |core count= | + | |core count=8 |
− | |thread count= | + | |thread count=8 |
|max cpus=1 | |max cpus=1 | ||
− | |max memory= | + | |max memory=64 GiB |
− | |||
− | |||
− | |||
− | |||
}} | }} | ||
− | '''Core i5-9500''' is a {{arch|64}} | + | '''Core i5-9500''' is a planned {{arch|64}} mid-range performance [[x86]] desktop processor by [[Intel]] set to be introduced in [[2018]]. The i5-9400 is fabricated on Intel's 2nd generation [[10 nm process|10nm+ process]] based on the {{intel|Ice Lake|l=arch}} microarchitecture. |
+ | |||
+ | |||
+ | {{unknown features}} | ||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/ice_lake#Memory_Hierarchy|l1=Ice Lake § Cache}} |
{{cache size | {{cache size | ||
− | |l1 cache= | + | |l1 cache=512 KiB |
− | |l1i cache= | + | |l1i cache=256 KiB |
− | |l1i break= | + | |l1i break=8x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
− | |l1d cache= | + | |l1d cache=256 KiB |
− | |l1d break= | + | |l1d break=8x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d policy=write-back | |l1d policy=write-back | ||
− | |l2 cache= | + | |l2 cache=2 MiB |
− | |l2 break= | + | |l2 break=8x256 KiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back | ||
− | |l3 cache= | + | |l3 cache=12 MiB |
− | |l3 break= | + | |l3 break=8x1.5 MiB |
|l3 desc=12-way set associative | |l3 desc=12-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
}} | }} |
Facts about "Core i5-9500 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-9500 - Intel#package + and Core i5-9500 - Intel#pcie + |
base frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Cannon Point + |
clock multiplier | 30 + |
core count | 6 + |
core family | 6 + |
core model | 158 + |
core name | Coffee Lake R + |
core stepping | U0 + |
designer | Intel + |
device id | 0x3E92 + |
die area | 149 mm² (0.231 in², 1.49 cm², 149,000,000 µm²) + |
family | Core i5 + |
first announced | April 23, 2019 + |
first launched | April 23, 2019 + |
full page name | intel/core i5/i5-9500 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Stable Image Platform Program + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel stable image platform program support | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | UHD Graphics 630 + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 1,100 MHz (1.1 GHz, 1,100,000 KHz) + |
integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 9 MiB (9,216 KiB, 9,437,184 B, 0.00879 GiB) + |
ldate | April 23, 2019 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Desktop + |
max cpu count | 1 + |
max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max memory | 131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) + |
max memory bandwidth | 39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) + |
max memory channels | 2 + |
microarchitecture | Coffee Lake + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | i5-9500 + |
name | Core i5-9500 + |
package | FCLGA-1151 + |
part number | CM8068403362610 + |
platform | Coffee Lake + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 192.00 (€ 172.80, £ 155.52, ¥ 19,839.36) + and $ 202.00 (€ 181.80, £ 163.62, ¥ 20,872.66) + |
release price (box) | $ 202.00 (€ 181.80, £ 163.62, ¥ 20,872.66) + |
release price (tray) | $ 192.00 (€ 172.80, £ 155.52, ¥ 19,839.36) + |
s-spec | SRF4B + |
series | i5-9000 + |
smp max ways | 1 + |
socket | LGA-1151 + |
supported memory type | DDR4-2666 + |
tdp | 65 W (65,000 mW, 0.0872 hp, 0.065 kW) + |
technology | CMOS + |
thread count | 6 + |
turbo frequency (1 core) | 4,400 MHz (4.4 GHz, 4,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |