From WikiChip
Editing intel/atom/z520pt
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Facts about "Atom Z520PT - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Atom Z520PT - Intel#package + |
base frequency | 1,333.33 MHz (1.333 GHz, 1,333,330 kHz) + |
bus rate | 533.33 MT/s (0.533 GT/s, 533,330 kT/s) + |
bus speed | 133.33 MHz (0.133 GHz, 133,330 kHz) + |
bus type | FSB + |
chipset | Poulsbo + |
clock multiplier | 10 + |
core count | 1 + |
core family | 6 + |
core model | 28 + |
core name | Silverthorne + |
core stepping | C0 + |
core voltage (max) | 1.1 V (11 dV, 110 cV, 1,100 mV) + |
core voltage (min) | 0.75 V (7.5 dV, 75 cV, 750 mV) + |
cpuid | 106C2 + |
designer | Intel + |
die area | 24.18 mm² (0.0375 in², 0.242 cm², 24,180,000 µm²) + |
die length | 7.8 mm (0.78 cm, 0.307 in, 7,800 µm) + |
die width | 3.1 mm (0.31 cm, 0.122 in, 3,100 µm) + |
family | Atom + |
first announced | March 2, 2009 + |
first launched | March 2, 2009 + |
full page name | intel/atom/z520pt + |
has feature | Hyper-Threading Technology + and Enhanced SpeedStep Technology + |
has intel enhanced speedstep technology | true + |
has locked clock multiplier | true + |
has simultaneous multithreading | true + |
instance of | microprocessor + |
isa | x86-32 + |
isa family | x86 + |
l1$ size | 56 KiB (57,344 B, 0.0547 MiB) + |
l1d$ description | 6-way set associative + |
l1d$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
ldate | March 2, 2009 + |
main image | + |
main image caption | Silverthorne chip + |
manufacturer | Intel + |
market segment | Mobile + |
max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max cpu count | 1 + |
max junction temperature | 383.15 K (110 °C, 230 °F, 689.67 °R) + |
max storage temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
microarchitecture | Bonnell + |
min case temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
min junction temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
model number | Z520PT + |
name | Atom Z520PT + |
package | FCBGA-437 + |
part number | CH80566EE014DT + |
platform | Menlow + |
power dissipation (average) | 0.22 W (220 mW, 2.9502e-4 hp, 2.2e-4 kW) + |
power dissipation (idle) | 0.1 W (100 mW, 1.341e-4 hp, 1.0e-4 kW) + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |
s-spec | SLGPP + |
series | Z500 + |
smp max ways | 1 + |
socket | BGA-437 + |
tdp | 2 W (2,000 mW, 0.00268 hp, 0.002 kW) + |
technology | CMOS + |
thread count | 2 + |
transistor count | 47,212,207 + |
word size | 32 bit (4 octets, 8 nibbles) + |