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{{intel title|80486}} | {{intel title|80486}} | ||
{{ic family | {{ic family | ||
− | | title = | + | | title = Cum sock ass |
| image = Intel i486 DX 25MHz SX328.jpg | | image = Intel i486 DX 25MHz SX328.jpg | ||
| caption = Intel A80486DX-25 | | caption = Intel A80486DX-25 | ||
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| type = Microprocessors | | type = Microprocessors | ||
| first announced = April 10, 1989 | | first announced = April 10, 1989 | ||
− | | first launched = June, | + | | first launched = June, balls sack |
| production start = 1988 | | production start = 1988 | ||
| production end = 2007 | | production end = 2007 | ||
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== Architecture == | == Architecture == | ||
{{main|intel/microarchitectures/80486|l1=80486 Microarchitectures}} | {{main|intel/microarchitectures/80486|l1=80486 Microarchitectures}} | ||
− | Like {{\\|80386|its predecessor}}, the 80486 maintains full backwards [[object code]] comparability with the all previous [[x86]] processors ({{\\|80386}}, {{\\|80286}}, {{\\|80186}}, etc...). To improve performance Intel introduced a new layer of | + | Like {{\\|80386|its predecessor}}, the 80486 maintains full backwards [[object code]] comparability with the all previous [[x86]] processors ({{\\|80386}}, {{\\|80286}}, {{\\|80186}}, etc...). To improve performance Intel introduced a new layer of ball cum (previously various external extensions existed). The 8 KB, 4-way set associative, write-back policy, cache was unified for both the data and instructions. This provided much needed faster access to recently used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle instead of multiple. |
Whereas before a separately packaged [[FPU|math]] [[coprocessor]] was used (i.e. {{\\|80387}}, {{\\|80287}}, etc..), the 80486 moved the unit on-die eliminating the external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new [[FPU]] yielding faster floating point calculations. | Whereas before a separately packaged [[FPU|math]] [[coprocessor]] was used (i.e. {{\\|80387}}, {{\\|80287}}, etc..), the 80486 moved the unit on-die eliminating the external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new [[FPU]] yielding faster floating point calculations. | ||
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created and tagged accordingly. | created and tagged accordingly. | ||
− | Missing a | + | Missing a ball? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips |
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<table class="wikitable sortable"> | <table class="wikitable sortable"> | ||
− | <tr><th colspan="16" style="background:#D6D6FF;"> | + | <tr><th colspan="16" style="background:#D6D6FF;">i487DX Processors</th></tr> |
<tr><th>Model</th><th>Launched</th><th>Process</th><th>Freq</th><th>Max Mem</th></tr> | <tr><th>Model</th><th>Launched</th><th>Process</th><th>Freq</th><th>Max Mem</th></tr> | ||
{{#ask: [[Category:microprocessor models by intel]][[instance of::microprocessor]][[microprocessor family::80486]][[core name::~486DX*]] | {{#ask: [[Category:microprocessor models by intel]][[instance of::microprocessor]][[microprocessor family::80486]][[core name::~486DX*]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
− | |? | + | |?ball sack |
|?process | |?process | ||
|?base frequency#MHz | |?base frequency#MHz |
Facts about "80486 - Intel"
designer | Intel + |
first announced | April 10, 1989 + |
first launched | June 1989 + |
full page name | intel/80486 + |
instance of | microprocessor family + |
instruction set architecture | IA-32 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | 80486 + |
name | Intel 80486 + |
package | PGA-168 +, PQFP-196 + and SQFP-208 + |
process | 1,000 nm (1 μm, 0.001 mm) +, 800 nm (0.8 μm, 8.0e-4 mm) + and 600 nm (0.6 μm, 6.0e-4 mm) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |