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Latest revision Your text
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|introduction=September 12, 2019
 
|introduction=September 12, 2019
 
|process=14 nm
 
|process=14 nm
−
|cores=9
+
|cores=12
−
|cores 2=10
 
−
|cores 3=11
 
−
|cores 4=12
 
 
|type=Superscalar
 
|type=Superscalar
 
|type 2=Pipelined
 
|type 2=Pipelined
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|speculative=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|renaming=Yes
−
|stages=17
 
−
|decode=6-way
 
 
|isa=z/Architecture
 
|isa=z/Architecture
 
|l1i=128 KiB
 
|l1i=128 KiB
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== Architecture ==
 
== Architecture ==
 
=== Key changes from {{\\|z14}} ===
 
=== Key changes from {{\\|z14}} ===
−
* Mainframe
+
* Scalability
 
** Up to 190-way multiprocessing (from 170-way)
 
** Up to 190-way multiprocessing (from 170-way)
 
** Less CPs per drawer (4, down from 6)
 
** Less CPs per drawer (4, down from 6)
 
** Less CPs per logical cluster (2, down from 3)
 
** Less CPs per logical cluster (2, down from 3)
 
** 1 more drawer (5, up from 4)
 
** 1 more drawer (5, up from 4)
−
** 0-12 PCIe+ I/O drawers (up from 0-5 drawers)
 
−
** Rack
 
−
*** standard 19" racks (from 24-inch racks)
 
−
*** 1-4 frame configs (up from only 2-frame configs)
 
−
*** rear only I/O and power connections (from front & rear)
 
−
 
−
 
 
* Central Processor (CP)
 
* Central Processor (CP)
 
** 2 more cores (12, up from 10)
 
** 2 more cores (12, up from 10)
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*** 960 MiB, 40-way set associative
 
*** 960 MiB, 40-way set associative
 
*** 64K sets, 256 B line size
 
*** 64K sets, 256 B line size
−
*** Non-exclusive (almost always inclusive, but not strictly)
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*** Non-exclusive
 
** System Memory
 
** System Memory
 
*** Up to 40 TiB
 
*** Up to 40 TiB
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== Overview ==
 
== Overview ==
−
Introduced in early September 2019, the z15 mainframe is the successor to the {{\\|z14}}. The z15 is designed to improve both single-thread and multi-core performance as well as introduce better data security features for pervasive encryption through new hardware acceleration.
+
 
  
 
{{work-in-progress}}
 
{{work-in-progress}}
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=== Mainframe ===
 
=== Mainframe ===
−
The z15 mainframe has changed from the z14 in a number of important ways. IBM switched from a 24-inch to standard 19-inch rack chassis, meaning they can now be incorporated into standard data center aisles. For this, IBM provides new options for hot and cold aisle configurations. Unlike the last few generations which came in only 2-frame options, the new z15 is intended to scale from one to four frames depending on the desired configuration. Additionally, the z15 comes with 1 to 5 CPC drawers.
+
{{empty section}}
−
 
 
−
==== Models ====
 
−
The z15 comes in a single model - T01. There are 5 feature codes.
 
−
 
 
−
{| class="wikitable"
 
−
|-
 
−
! colspan="9" | z15 T01 Configurations
 
−
|-
 
−
! Feature<br>Code !! Feature<br>Name !! CPC Drawers !! Core !! Spare Cores !! SAPs !! Memory !! Frequency !! Max PCIe<br>fanout
 
−
|-
 
−
| 0655 || Max34 || 1 || 34 || 2 || 4 || 512 GiB - 7.75 TiB || 5.2 GHz || 12
 
−
|-
 
−
| 0656 || Max71 || 2 || 71 || 2 || 8 || 512 GiB - 15.75 TiB || 5.2 GHz || 24
 
−
|-
 
−
| 0657 || Max108 || 3 || 108 || 2 || 12 || 512 GiB - 23.75 TiB || 5.2 GHz || 36
 
−
|-
 
−
| 0658 || Max145 || 4 || 145 || 2 || 16 || 512 GiB - 31.75 TiB || 5.2 GHz || 48
 
−
|-
 
−
| 0659 || Max190 || 5 || 190 || 2 || 22 || 512 GiB - 39.75 TiB || 5.2 GHz || 60
 
−
|}
 
−
 
 
−
Note that the z15 reserves a fixed amount of 256 GiB (0.25 TiB) for the hardware system area (HSA).
 
−
 
 
−
==== Frames ====
 
−
The z15 supports anywhere from one to four frames. The frames are labeled Z, A, B, and C.
 
−
 
 
−
{{expand section}}
 
  
 
== System ==
 
== System ==
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=== Drawer ===
 
=== Drawer ===
−
{{empty section}}
 
−
 
−
=== Hardware system area (HSA) ===
 
 
{{empty section}}
 
{{empty section}}
  
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** 17 metal layers
 
** 17 metal layers
 
* 9,200,000,000 transistors
 
* 9,200,000,000 transistors
−
** 15.6 miles of wire
 
−
** 26,200,000,000 wire connections
 
 
* 5.2 GHz
 
* 5.2 GHz
 
* 12 cores
 
* 12 cores
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* [[14 nm process|14HP FinFET on SOI]]
 
* [[14 nm process|14HP FinFET on SOI]]
 
** 17 metal layers
 
** 17 metal layers
−
* 12,200,000,000 transistors
+
* 9,700,000,000 billion transistors (''note that this number, from the technical document, is likely incorrect as it's the same number as the z14'')
−
** ~20,000 C4s
 
−
** 13.5 miles of signal wire
 
 
* 960 MiB shared [[eDRAM]] [[L4 cache]].
 
* 960 MiB shared [[eDRAM]] [[L4 cache]].
 
* Die size
 
* Die size

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Facts about "z15 - Microarchitectures - IBM"
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codenamez15 +
core count12 +, 9 +, 10 + and 11 +
designerIBM +
first launchedSeptember 12, 2019 +
full page nameibm/microarchitectures/z15 +
instance ofmicroarchitecture +
instruction set architecturez/Architecture +
manufacturerGlobalFoundries +
microarchitecture typeCPU +
namez15 +
pipeline stages17 +
process14 nm (0.014 μm, 1.4e-5 mm) +