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|introduction=September 12, 2019 | |introduction=September 12, 2019 | ||
|process=14 nm | |process=14 nm | ||
| − | |cores | + | |cores=12 |
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|type=Superscalar | |type=Superscalar | ||
|type 2=Pipelined | |type 2=Pipelined | ||
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|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
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|isa=z/Architecture | |isa=z/Architecture | ||
|l1i=128 KiB | |l1i=128 KiB | ||
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== Architecture == | == Architecture == | ||
=== Key changes from {{\\|z14}} === | === Key changes from {{\\|z14}} === | ||
| − | * | + | * Higher scalability |
** Up to 190-way multiprocessing (from 170-way) | ** Up to 190-way multiprocessing (from 170-way) | ||
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* Central Processor (CP) | * Central Processor (CP) | ||
** 2 more cores (12, up from 10) | ** 2 more cores (12, up from 10) | ||
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**** Larger vector physical register files (???, up from 127 entries) | **** Larger vector physical register files (???, up from 127 entries) | ||
*** Execution engine | *** Execution engine | ||
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**** New Modulo Arithmetic (MA) unit | **** New Modulo Arithmetic (MA) unit | ||
*** Memory subsystem | *** Memory subsystem | ||
**** 2x larger [[L2]] [[instruction cache]] (4 MiB, up from 2 MiB) | **** 2x larger [[L2]] [[instruction cache]] (4 MiB, up from 2 MiB) | ||
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** Shared L3 | ** Shared L3 | ||
*** 2x larger [[L3]] (256 MiB, up from 128 MiB) | *** 2x larger [[L3]] (256 MiB, up from 128 MiB) | ||
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*** X Bus removed (2 interface, down from 3) | *** X Bus removed (2 interface, down from 3) | ||
*** New PCIe Gen interface (3 interfaces, up from 2) | *** New PCIe Gen interface (3 interfaces, up from 2) | ||
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** New integration | ** New integration | ||
*** Nest Acceleration Unit (NXU) | *** Nest Acceleration Unit (NXU) | ||
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* System Controller (SC) | * System Controller (SC) | ||
** 1.4x Larger L4 cache (960 MiB, up from 672 MiB) | ** 1.4x Larger L4 cache (960 MiB, up from 672 MiB) | ||
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=== Block Diagram === | === Block Diagram === | ||
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:[[File:z15 block diagram.svg|900px]] | :[[File:z15 block diagram.svg|900px]] | ||
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{{work-in-progress}} | {{work-in-progress}} | ||
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=== Mainframe === | === Mainframe === | ||
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== System == | == System == | ||
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=== Drawer === | === Drawer === | ||
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{{empty section}} | {{empty section}} | ||
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** 17 metal layers | ** 17 metal layers | ||
* 9,200,000,000 transistors | * 9,200,000,000 transistors | ||
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* 5.2 GHz | * 5.2 GHz | ||
* 12 cores | * 12 cores | ||
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| − | :[[File:z15_cp_floorplan.png | + | :[[File:z15_cp_floorplan.png|500px]] |
==== Core ==== | ==== Core ==== | ||
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* [[14 nm process|14HP FinFET on SOI]] | * [[14 nm process|14HP FinFET on SOI]] | ||
** 17 metal layers | ** 17 metal layers | ||
| − | * | + | * 9,700,000,000 billion transistors (''note that this number, from the technical document, is likely incorrect as it's the same number as the z14'') |
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* 960 MiB shared [[eDRAM]] [[L4 cache]]. | * 960 MiB shared [[eDRAM]] [[L4 cache]]. | ||
* Die size | * Die size | ||
Facts about "z15 - Microarchitectures - IBM"
| codename | z15 + |
| core count | 12 +, 9 +, 10 + and 11 + |
| designer | IBM + |
| first launched | September 12, 2019 + |
| full page name | ibm/microarchitectures/z15 + |
| instance of | microarchitecture + |
| instruction set architecture | z/Architecture + |
| manufacturer | GlobalFoundries + |
| microarchitecture type | CPU + |
| name | z15 + |
| pipeline stages | 17 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |