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|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=core | |l1i per=core | ||
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|l1d=32 KiB | |l1d=32 KiB | ||
|l1d per=core | |l1d per=core | ||
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|l2=512 KiB | |l2=512 KiB | ||
− | |l2 per=core | + | |l2 per=core |
− | + | |l3=120 MiB | |
− | |l3= | + | |l3 per=chip |
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|predecessor=POWER8+ | |predecessor=POWER8+ | ||
|predecessor link=ibm/microarchitectures/power8+ | |predecessor link=ibm/microarchitectures/power8+ | ||
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}} | }} | ||
'''POWER9''' is [[IBM]]'s successor to {{\\|POWER8}}, a [[14 nm]] microarchitecture for [[Power]]-based server microprocessors first introduced in the 2nd half of [[2017]]. POWER9-based processors are branded under the {{ibm|POWER}} family. | '''POWER9''' is [[IBM]]'s successor to {{\\|POWER8}}, a [[14 nm]] microarchitecture for [[Power]]-based server microprocessors first introduced in the 2nd half of [[2017]]. POWER9-based processors are branded under the {{ibm|POWER}} family. | ||
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== Process Technology == | == Process Technology == | ||
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== Introduction == | == Introduction == | ||
− | IBM introduced the POWER9 scale out variant of POWER in December 2017. Scale up POWER9 processors were introduced in August 2018. | + | IBM introduced the POWER9 scale out variant of POWER in December 2017. Scale up POWER9 processors were introduced in August 2018. A third variant for high I/O will be introduced in 2019. |
== Compatibility == | == Compatibility == | ||
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** L1I Cache | ** L1I Cache | ||
*** 32 [[KiB]], 8-way set associative | *** 32 [[KiB]], 8-way set associative | ||
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*** Per SMT4 Core | *** Per SMT4 Core | ||
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** L1D Cache | ** L1D Cache | ||
*** 32 KiB, 8-way set associative | *** 32 KiB, 8-way set associative | ||
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*** Per SMT4 Core | *** Per SMT4 Core | ||
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** L2 Cache | ** L2 Cache | ||
− | *** | + | *** 258 KiB per SMT4 core |
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** L3 Cache | ** L3 Cache | ||
*** 120 MiB [[eDRAM]] | *** 120 MiB [[eDRAM]] | ||
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*** 12 chunks (regions) of 10 MiB 20-way set associative | *** 12 chunks (regions) of 10 MiB 20-way set associative | ||
*** 7 TB/s on-chip bandwidth | *** 7 TB/s on-chip bandwidth | ||
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* 17-layer metal stack | * 17-layer metal stack | ||
* 8,000,000,000 transistors | * 8,000,000,000 transistors | ||
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* 693.37 mm² die size | * 693.37 mm² die size | ||
* 25.228 mm x 27.48416 mm | * 25.228 mm x 27.48416 mm | ||
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* 17-layer metal stack | * 17-layer metal stack | ||
* 8,000,000,000 transistors | * 8,000,000,000 transistors | ||
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* 693.37 mm² die size | * 693.37 mm² die size | ||
* 25.228 mm x 27.48416 mm | * 25.228 mm x 27.48416 mm | ||
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[[File:power9 su die (annotated).png|600px]] | [[File:power9 su die (annotated).png|600px]] | ||
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== Bibliography == | == Bibliography == | ||
− | * {{ | + | * {{hcbib|28}} |
− | * {{ | + | * {{hcbib|30}} |
== See also == | == See also == |
Facts about "POWER9 - Microarchitectures - IBM"
codename | POWER9 + |
core count | 24 +, 4 +, 8 +, 12 +, 16 + and 20 + |
designer | IBM + |
first launched | August 2017 + |
full page name | ibm/microarchitectures/power9 + |
instance of | microarchitecture + |
instruction set architecture | Power ISA v3.0B + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | POWER9 + |
phase-out | 2020 + |
pipeline stages (max) | 16 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |