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|manufacturer=GlobalFoundries | |manufacturer=GlobalFoundries | ||
|introduction=August, 2017 | |introduction=August, 2017 | ||
− | |phase-out= | + | |phase-out=August, 2018 |
|process=14 nm | |process=14 nm | ||
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|predecessor=POWER8+ | |predecessor=POWER8+ | ||
|predecessor link=ibm/microarchitectures/power8+ | |predecessor link=ibm/microarchitectures/power8+ | ||
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}} | }} | ||
'''POWER9''' is [[IBM]]'s successor to {{\\|POWER8}}, a [[14 nm]] microarchitecture for [[Power]]-based server microprocessors first introduced in the 2nd half of [[2017]]. POWER9-based processors are branded under the {{ibm|POWER}} family. | '''POWER9''' is [[IBM]]'s successor to {{\\|POWER8}}, a [[14 nm]] microarchitecture for [[Power]]-based server microprocessors first introduced in the 2nd half of [[2017]]. POWER9-based processors are branded under the {{ibm|POWER}} family. | ||
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== Process Technology == | == Process Technology == | ||
POWER9-based microprocessors are fabricated on [[GlobalFoundries]]'s High-Performance [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process. The process was designed by IBM at what used to be their East Fishkill, New York fab which has since been sold to GlobalFoundries. | POWER9-based microprocessors are fabricated on [[GlobalFoundries]]'s High-Performance [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process. The process was designed by IBM at what used to be their East Fishkill, New York fab which has since been sold to GlobalFoundries. | ||
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== Compatibility == | == Compatibility == | ||
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! Compiler !! CPU !! Arch-Favorable | ! Compiler !! CPU !! Arch-Favorable | ||
|- | |- | ||
− | | [[GCC]] || style="background-color: #ffdad6;" | <code>-mcpu= | + | | [[GCC]] || style="background-color: #ffdad6;" | <code>-mcpu=pwr9</code> || style="background-color: #ffdad6;" | <code>-mtune=pwr9</code> |
|- | |- | ||
− | | [[LLVM]] || <code>-mcpu= | + | | [[LLVM]] || <code>-mcpu=pwr9</code> || style="background-color: #ffdad6;" | <code>-mtune=pwr9</code> |
|- | |- | ||
| {{ibm|XL C/C++}} || <code>-mcpu=pwr9</code> || <code>-mtune=pwr9</code> | | {{ibm|XL C/C++}} || <code>-mcpu=pwr9</code> || <code>-mtune=pwr9</code> | ||
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*** [[eDRAM]] | *** [[eDRAM]] | ||
*** 7 TB/s on-chip bandwidth | *** 7 TB/s on-chip bandwidth | ||
+ | * Memory | ||
+ | ** Scale-up | ||
+ | *** Dropped support for CDIMM | ||
* Hardware Acceleration | * Hardware Acceleration | ||
** {{ibm|PowerAXON}} | ** {{ibm|PowerAXON}} | ||
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** L1I Cache | ** L1I Cache | ||
*** 32 [[KiB]], 8-way set associative | *** 32 [[KiB]], 8-way set associative | ||
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*** Per SMT4 Core | *** Per SMT4 Core | ||
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** L1D Cache | ** L1D Cache | ||
*** 32 KiB, 8-way set associative | *** 32 KiB, 8-way set associative | ||
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*** Per SMT4 Core | *** Per SMT4 Core | ||
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** L2 Cache | ** L2 Cache | ||
− | *** | + | *** 258 KiB per SMT4 core |
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** L3 Cache | ** L3 Cache | ||
*** 120 MiB [[eDRAM]] | *** 120 MiB [[eDRAM]] | ||
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*** 12 chunks (regions) of 10 MiB 20-way set associative | *** 12 chunks (regions) of 10 MiB 20-way set associative | ||
*** 7 TB/s on-chip bandwidth | *** 7 TB/s on-chip bandwidth | ||
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POWER9 succeeds {{\\|POWER8}}, introducing many core enhancements as well as large architectural changes. POWER9 has taken a highly modular design approach, with the same design supporting up to 12 [[physical cores|cores]] with 96 [[logical cores|threads]] (SMT8) or up to 24 cores with 96 threads (SMT4). IBM offers POWER9 as both [[scale up]] and [[scale out]] solutions. In total, there are four targeted chip implementations (24C/SO, 24C/SU, 12C/SO, and 12C/SU). | POWER9 succeeds {{\\|POWER8}}, introducing many core enhancements as well as large architectural changes. POWER9 has taken a highly modular design approach, with the same design supporting up to 12 [[physical cores|cores]] with 96 [[logical cores|threads]] (SMT8) or up to 24 cores with 96 threads (SMT4). IBM offers POWER9 as both [[scale up]] and [[scale out]] solutions. In total, there are four targeted chip implementations (24C/SO, 24C/SU, 12C/SO, and 12C/SU). | ||
+ | === Variations === | ||
POWER9 comes in two flavors - [[scale out]] (SO) and [[scale up]] (SU). The scale out variations are designed for traditional datacenter clusters utilizing [[uniprocessor|single-socket]] and [[multiprocessor|dual-socket]] setups. The Scale-Up variations are designed for [[NUMA]] servers with four or more sockets, supporting large amounts of memory capacity and throughput. | POWER9 comes in two flavors - [[scale out]] (SO) and [[scale up]] (SU). The scale out variations are designed for traditional datacenter clusters utilizing [[uniprocessor|single-socket]] and [[multiprocessor|dual-socket]] setups. The Scale-Up variations are designed for [[NUMA]] servers with four or more sockets, supporting large amounts of memory capacity and throughput. | ||
− | === Scale out === | + | ==== Scale out ==== |
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For the scale out there are two variations, a [[12-core]] SMT8 model and a [[24-core]] SMT4 model. The SMT4 is optimized for the Linux ecosystem whereas the SMT8 model is said to be optimized for the [[PowerVM]] ecosystem ({{ibm|AIX}} / {{ibm|IBM i}} customers). Those models support up to 8 channels of [[DDR4]] memory for up to 4 [[TiB]] of DDR4-2667 memory (per socket). Those models offer up to 120 GiB/s of sustained bandwidth. | For the scale out there are two variations, a [[12-core]] SMT8 model and a [[24-core]] SMT4 model. The SMT4 is optimized for the Linux ecosystem whereas the SMT8 model is said to be optimized for the [[PowerVM]] ecosystem ({{ibm|AIX}} / {{ibm|IBM i}} customers). Those models support up to 8 channels of [[DDR4]] memory for up to 4 [[TiB]] of DDR4-2667 memory (per socket). Those models offer up to 120 GiB/s of sustained bandwidth. | ||
Scale out processors have 48 {{ibm|PowerAXON}} lines (x48) and come with two [[SMP links]]. | Scale out processors have 48 {{ibm|PowerAXON}} lines (x48) and come with two [[SMP links]]. | ||
− | === Scale up === | + | ==== Scale up ==== |
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The POWER9 [[scale up]] is designed for their enterprise servers and come with two variations, a [[12-core]] SMT8 model and a [[24-core]] SMT4 model. The SMT4 is optimized for Linux Ecosystem whereas the SMT8 is said to be optimized for the [[PowerVM]] Ecosystem community ({{ibm|AIX}} / {{ibm|IBM i}} customers). POWER9 inherits the same buffered memory architecture first introduced with {{\\|POWER8}}. POWER9 has two memory controllers capable of driving four differential memory interface (DMI) channels, each with a maximum signaling rate of 9.6 GT/s for a sustained bandwidth of up to 28.8 GB/s. Each of the DMI channels connects to one dedicated {{ibm|Centaur}} memory buffer chip which, in turn, provides four DDR4 memory channels running at up to 3200 MT/s as well as 16 MiB of L4 cache. All in all, POWER9 scale-up can use eight buffered memory channels to access up to 32 channels of DDR memory and provides an additional 128 MiB of level 4 cache. | The POWER9 [[scale up]] is designed for their enterprise servers and come with two variations, a [[12-core]] SMT8 model and a [[24-core]] SMT4 model. The SMT4 is optimized for Linux Ecosystem whereas the SMT8 is said to be optimized for the [[PowerVM]] Ecosystem community ({{ibm|AIX}} / {{ibm|IBM i}} customers). POWER9 inherits the same buffered memory architecture first introduced with {{\\|POWER8}}. POWER9 has two memory controllers capable of driving four differential memory interface (DMI) channels, each with a maximum signaling rate of 9.6 GT/s for a sustained bandwidth of up to 28.8 GB/s. Each of the DMI channels connects to one dedicated {{ibm|Centaur}} memory buffer chip which, in turn, provides four DDR4 memory channels running at up to 3200 MT/s as well as 16 MiB of L4 cache. All in all, POWER9 scale-up can use eight buffered memory channels to access up to 32 channels of DDR memory and provides an additional 128 MiB of level 4 cache. | ||
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* 17-layer metal stack | * 17-layer metal stack | ||
* 8,000,000,000 transistors | * 8,000,000,000 transistors | ||
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* 693.37 mm² die size | * 693.37 mm² die size | ||
* 25.228 mm x 27.48416 mm | * 25.228 mm x 27.48416 mm | ||
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* 17-layer metal stack | * 17-layer metal stack | ||
* 8,000,000,000 transistors | * 8,000,000,000 transistors | ||
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* 693.37 mm² die size | * 693.37 mm² die size | ||
* 25.228 mm x 27.48416 mm | * 25.228 mm x 27.48416 mm | ||
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[[File:power9 su die (annotated).png|600px]] | [[File:power9 su die (annotated).png|600px]] | ||
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== Bibliography == | == Bibliography == | ||
− | * {{ | + | * {{hcbib|28}} |
− | * {{ | + | * {{hcbib|30}} |
== See also == | == See also == |
Facts about "POWER9 - Microarchitectures - IBM"
codename | POWER9 + |
core count | 24 +, 4 +, 8 +, 12 +, 16 + and 20 + |
designer | IBM + |
first launched | August 2017 + |
full page name | ibm/microarchitectures/power9 + |
instance of | microarchitecture + |
instruction set architecture | Power ISA v3.0B + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | POWER9 + |
phase-out | 2020 + |
pipeline stages (max) | 16 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |