Editing hisilicon/k3/k3v2e

{{hisilicon title|K3V2E}}
{{chip
|name=K3V2E
|no image=Yes
|designer=HiSilicon
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=K3V2E
|part number=Hi3620
|market=Mobile
|first announced=2013
|first launched=2013
|family=K3
|frequency=1,500 MHz
|isa=ARMv7
|isa family=ARM
|microarch=Cortex-A9
|core name=Cortex-A9
|process=40 nm
|transistors=600,000,000
|technology=CMOS
|word size=32 bit
|core count=4
|thread count=4
|max cpus=1
|package module 1={{packages/hisilicon/tfbga-576}}
}}
'''K3V2E''' is a {{arch|32}} [[quad-core]] mobile [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2013]]. This chip, which is fabricated on a [[40 nm process]], incorporates four {{armh|Cortex-A9|l=arch}} cores operating at 1.5 GHz. The K3V2 integrated [[Vivante]]'s {{vivante|GC4000}} (16 cores) [[IGP]] and supports up to 2 channels of LPDDR2-900 memory. The K3V2E is an enhanced version of the {{\\|K3V2}}, although the exact changes are not well-documented.



== Cache ==
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
{{cache size
|l1 cache=256 KiB
|l1i cache=128 KiB
|l1i break=4x32 KiB
|l1i desc=4-way set associative
|l1d cache=128 KiB
|l1d break=4x32 KiB
|l1d desc=4-way set associative
|l2 cache=1 MiB
|l2 break=1x1 MiB
|l2 desc=8-way set associative
}}

== Memory controller ==
{{memory controller
|type=LPDDR2-900
|ecc=No
|controllers=1
|channels=2
|width=32 bit
|max bandwidth=6.71 GiB/s
|bandwidth schan=3.35 GiB/s
|bandwidth dchan=6.71 GiB/s
}}

== Graphics ==
{{integrated graphics
| gpu                 = GC4000
| designer            = Vivante
| execution units     = 16
| max displays        = 1
| frequency           = 480 MHz

| output crt          = 
| output sdvo         = 
| output dsi          = Yes
| output edp          = 
| output dp           = 
| output hdmi         = 
| output vga          = 
| output dvi          = 

| directx ver        = 11
| opengl es ver      = 3.1
| openvg ver         = 1.1
| opencl ver         = 1.2
| opengl ver         = 3.0

| max res dsi        = 1920x1200
| max res dsi freq   = 
}}

== Expansions ==
* 4x high-speed UART interfaces
* 2x SPI
* 2x I2C + 2x I2C for camera
* USB 2.0 On-The-Go (HS OTG) PHY
* USB 1.1
* 2x MMC/SD/SDIO interface
* 22x GPIOs
* 10 Timers

== Block Diagram ==
[[File:hisilicon k3v2 block.png|700px]]

== Utilizing devices ==
* [[used by::Huawei HN3-U01]]
* [[used by::Huawei Ascend P6]] (P6-C00)
* [[used by::Ascend W2]] (W2‐T00)
* [[used by::Huawei Honor 3]]

{{expand list}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	K3V2E - HiSilicon#package +
base frequency	1,500 MHz (1.5 GHz, 1,500,000 kHz) +
core count	4 +
core name	Cortex-A9 +
designer	HiSilicon + and ARM Holdings +
family	K3 +
first announced	2013 +
first launched	2013 +
full page name	hisilicon/k3/k3v2e +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	GC4000 +
integrated gpu base frequency	480 MHz (0.48 GHz, 480,000 KHz) +
integrated gpu designer	Vivante +
integrated gpu execution units	16 +
isa	ARMv7 +
isa family	ARM +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	4-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	4-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	2013 +
manufacturer	TSMC +
market segment	Mobile +
max cpu count	1 +
max memory bandwidth	6.71 GiB/s (6,871.04 MiB/s, 7.205 GB/s, 7,204.808 MB/s, 0.00655 TiB/s, 0.0072 TB/s) +
max memory channels	2 +
microarchitecture	Cortex-A9 +
model number	K3V2E +
name	K3V2E +
package	TFBGA-576 +
part number	Hi3620 +
process	40 nm (0.04 μm, 4.0e-5 mm) +
smp max ways	1 +
supported memory type	LPDDR2-900 +
technology	CMOS +
thread count	4 +
transistor count	600,000,000 +
used by	Huawei HN3-U01 +, Huawei Ascend P6 +, Ascend W2 + and Huawei Honor 3 +
word size	32 bit (4 octets, 8 nibbles) +