Editing fujitsu/sparc64/sparc64 xii

{{fujitsu title|SPARC64 XII}}
{{chip
| name                = SPARC64 XII
| image               = sparc64 xii.png
| image size          = 250px
| caption             = SPARC64 XII Chip
| designer            = Fujitsu
| manufacturer        = TSMC
| model number        = SPARC64 XII
| part number         = 
| part number 2       = 
| market              = Server
| first announced     = 2015
| first launched      = April 4, 2017
| last order          = 
| last shipment       = 
| release price       = 

| family              = SPARC64
| series              = 
| locked              = 
| frequency           = 4,250 MHz
| bus type            = 
| bus speed           = 
| bus rate            = 
| bus links           = 
| clock multiplier    =

| isa family          = SPARC 
| isa                 = SPARC V9
| microarch           = SPARC64 XII
| platform            = 
| chipset             = 
| chipset 2           = 
| core name           = 
| core family         = 
| core model          = 
| core stepping       = 
| process             = 20 nm
| transistors         = 
| technology          = CMOS
| die area            = <!-- XX mm² -->
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 12
| thread count        = 96
| max cpus            = 32
| max memory          = 2 TiB

| electrical          = <!-- put Yes if electrical info is added -->
| power               = <!-- power consumption  -->
| average power       = 
| idle power          = 
| v core              = 
| v core tolerance    = <!-- OR ... -->
| v core min          = 
| v core max          = 
| v io                = 
| v io tolerance      = 
| v io 2              = <!-- OR ... -->
| v io 3              = 
| sdp                 = 
| tdp                 = 
| tdp typical         = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = <!-- use TJ/TC whenever possible instead -->
| temp max            = 
| tjunc min           = <!-- .. °C -->
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 
| tambient min        = 
| tambient max        = 

| packaging           = <!-- put Yes if packaging info is added -->
| package 0           = 
| package 0 type      = 
| package 0 pins      = 
| package 0 pitch     = 
| package 0 width     = 
| package 0 length    = 
| package 0 height    = 
| socket 0            = 
| socket 0 type       = 
| socket 0 2          = 
| socket 0 2 type     = 
| socket 0 3          = 
| socket 0 3 type     = 
| package 1           = 
| package 1 type      = 
| package 1 pins      = 
| package 1 pitch     = 
| package 1 width     = 
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| socket 1            = 
| socket 1 type       = 
}}
[[File:sparc64 xii wafer.jpg|right|thumb|XII Wafer]][[File:m12-2s.png|right|thumb|M12-2S server using SPARC64 XII]]
'''SPARC64 XII''' is a high-performance {{arch|64}} [[dodeca-core]] [[SPARC]] microprocessor designed by [[Fujitsu]] and introduced in April [[2017]].

== Cache ==
{{empty section}}

== Expansions ==
{{empty section}}

== Die Shot ==
* [[20 nm process]]

[[File:sparc64 xii die shot.png|600px]]


[[File:sparc64 xii die shot (annotated).png|600px]]
base frequency	4,250 MHz (4.25 GHz, 4,250,000 kHz) +
core count	12 +
designer	Fujitsu +
family	SPARC64 +
first announced	2015 +
first launched	April 4, 2017 +
full page name	fujitsu/sparc64/sparc64 xii +
instance of	microprocessor +
isa	SPARC V9 +
isa family	SPARC +
ldate	April 4, 2017 +
main image	+
main image caption	SPARC64 XII Chip +
manufacturer	TSMC +
market segment	Server +
max cpu count	32 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
microarchitecture	SPARC64 XII +
model number	SPARC64 XII +
name	SPARC64 XII +
process	20 nm (0.02 μm, 2.0e-5 mm) +
smp max ways	32 +
technology	CMOS +
thread count	96 +
word size	64 bit (8 octets, 16 nibbles) +