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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping | ||
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− | | rowspan="2" | Centaur CNS || 0 || 0x6 || 0x4 || 0x7 || | + | | rowspan="2" | Centaur CNS || 0 || 0x6 || 0x4 || 0x7 || 0x1 |
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− | | colspan="5" | Family 6 Model 71 Stepping | + | | colspan="5" | Family 6 Model 71 Stepping 1 |
|} | |} | ||
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== Architecture == | == Architecture == | ||
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=== Instruction set === | === Instruction set === | ||
− | The CHA SoC integrates up to eight cores, each featuring the {{x86|x86-64}} [[ISA]] along with | + | The CHA SoC integrates up to eight cores, each featuring the {{x86|x86-64}} [[ISA]] along with fullowing {{x86|extensions}}: |
{| class="wikitable" | {| class="wikitable" | ||
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== Overview == | == Overview == | ||
[[File:cha soc overview.svg|thumb|right|CHA Overview]] | [[File:cha soc overview.svg|thumb|right|CHA Overview]] | ||
− | Announced in 2019 and expected to be introduced in 2020, '''CHA''' (pronounced ''C-H-A'') is a new ground-up [[x86]] SoC designed by [[Centaur]] for the server, edge, and AI market. Fabricated on TSMC [[16 nm process]], the chip integrates eight high-performance [[x86]] "CNS" cores along with a brand new clean-sheet design "NCORE" [[neural processor]]. | + | Announced in 2019 and expected to be introduced in 2020, '''CHA''' (pronounced ''C-H-A'') is a new ground-up [[x86]] SoC designed by [[Centaur]] for the server, edge, and AI market. Fabricated on TSMC [[16 nm process]], the chip integrates eight high-performance [[x86]] "CNS" cores along with a brand new clean-sheet design high-performance "NCORE" [[neural processor]]. This is the first server x86 chip to integrate an AI [[accelerator]]. The integrated NPU is designed to allow for a reduction of platform cost by offering an AI inference coprocessor "free" on-die along with the standard server-class x86 cores. For many workloads, this accelerator means it's no longer required to add a third-party PCIe-based [[accelerator card]] unless a considerably higher performance is required. |
− | + | The CHA SoC features new CNS cores which introduce considerably higher [[single-thread performance]]. The cores also introduce the {{x86|AVX-512}} extension in order to offer better performance and more flexibility. | |
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+ | CHA is a fully integrated SoC. It incorporates both the [[source bridge]] and [[north bridge]] on-die. The chip supports for up to quad-channel [[DDR4 memory]] and up to 44 PCIe Gen 3 lanes. Additionally, the southbridge provides all the usual legacy I/O functionality. Additionally, CHA supports the ability to directly link to a second CHA SoC in a 2-way [[multiprocessing]] configuration. All the cores, along with the NCORE, the southbridge, and memory controller are all [[ring interconnect|interconnected on a ring]]. | ||
== CNS Core == | == CNS Core == | ||
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Each cycle, up to 32 bytes (half a line) of the instruction stream are fetched from the [[instruction cache]] into the instruction pre-decode queue. Since [[x86]] instructions may range from a single byte to 15 bytes, this buffer receives an unstructured byte stream which is then marked at the instruction boundary. In addition to marking instruction boundaries, the pre-decode also does various prefix processing. From the pre-decode queue, up to five individual instructions are fed into the formatted instruction queue (FIQ). | Each cycle, up to 32 bytes (half a line) of the instruction stream are fetched from the [[instruction cache]] into the instruction pre-decode queue. Since [[x86]] instructions may range from a single byte to 15 bytes, this buffer receives an unstructured byte stream which is then marked at the instruction boundary. In addition to marking instruction boundaries, the pre-decode also does various prefix processing. From the pre-decode queue, up to five individual instructions are fed into the formatted instruction queue (FIQ). | ||
− | Prior to getting sent to decode, the FIQ has the ability to do [[macro- | + | Prior to getting sent to decode, the FIQ has the ability to do [[macro-fusion]]. CNS can detect certain pairs of adjacent instructions such as a simple arithmetic operation followed by a conditional jump and couple them together such that they get decoded at the same time into a fused operation. This was improved further with the new CNS core. |
[[File:cns decode.svg|right|500px]] | [[File:cns decode.svg|right|500px]] | ||
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==== Neural processing unit (NPU) ==== | ==== Neural processing unit (NPU) ==== | ||
Each cycle, the neural processing unit reads data out of one or two of the four registers in the neural data unit. Alternatively, input data can also be moved from one neural register to the next. This is designed to efficiently handle fully connected neural networks. The neural processing unit (NPU) does various computations such as MAC operations, shifting, min/max, and various other functions designed to add flexibility in terms of support in preparation for future AI functionalities and operations. There is also extensive support for predication with 8 predication registers. The unit is optimized for 8-bit integers (9-bit calculations) but can also operate on [[16-bit integers]] as well as [[bfloat16]]. Wider [[data types]] allow for higher precision but they incur a latency penalty. 8-bit operations can be done in a single cycle while 16-bit integer and floating-point operations require three cycles to complete. The neural processing unit incorporates a 32-bit 4K accumulator which can operate in both 32b-integer and 32b-[[floating-point]] modes. The accumulator saturates on overflows to prevent wrap-around (e.g., the biggest positive to biggest negative). Following the millions or billions of repeated MAC operations, the output is sent to the output unit for post-processing. | Each cycle, the neural processing unit reads data out of one or two of the four registers in the neural data unit. Alternatively, input data can also be moved from one neural register to the next. This is designed to efficiently handle fully connected neural networks. The neural processing unit (NPU) does various computations such as MAC operations, shifting, min/max, and various other functions designed to add flexibility in terms of support in preparation for future AI functionalities and operations. There is also extensive support for predication with 8 predication registers. The unit is optimized for 8-bit integers (9-bit calculations) but can also operate on [[16-bit integers]] as well as [[bfloat16]]. Wider [[data types]] allow for higher precision but they incur a latency penalty. 8-bit operations can be done in a single cycle while 16-bit integer and floating-point operations require three cycles to complete. The neural processing unit incorporates a 32-bit 4K accumulator which can operate in both 32b-integer and 32b-[[floating-point]] modes. The accumulator saturates on overflows to prevent wrap-around (e.g., the biggest positive to biggest negative). Following the millions or billions of repeated MAC operations, the output is sent to the output unit for post-processing. | ||
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==== Output unit ==== | ==== Output unit ==== | ||
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=== Communication === | === Communication === | ||
− | There are a number of ways the NCORE can be communicated with. The individual CNS cores can directly read and write to the NCORE using the | + | There are a number of ways the NCORE can be communicated with. The individual CNS cores can directly read and write to the NCORE using the virtual address space (e.g., <code>open()</code>). AVX512 mov operations can also be used. The cores can also read the control and status registers. In turn, the NCORE can interrupt back to the core for follow-up post-processing. The two DMA controllers in the NCORE are also capable of communicating with the cache slices in the cores, the DRAM controllers, and optionally, other PCIe I/O devices. |
=== Instructions === | === Instructions === | ||
− | + | Instructions are 128-bit wide and execute in 1 clock cycle (including 0-cycle branches). Most instructions typically require 64-80 bits (roughly 1/2-3/4). Detailed definitions of the instructions are not made public as they are designed to be highly hardware-dependent designed for software to simplify the hardware and extract additional power efficiency. To that end, the instructions will likely change with new hardware versions. | |
* 30b: control of 2 RAM read & index operations | * 30b: control of 2 RAM read & index operations | ||
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== Die == | == Die == | ||
=== SoC === | === SoC === | ||
− | * [[TSMC]] [[16 nm process]] | + | * [[TSMC]] [[16 nm process]] |
* 194 mm² | * 194 mm² | ||
− | :[[File: | + | :[[File:cha soc.png|600px|class=wikichip_ogimage]] |
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=== Core group === | === Core group === | ||
− | : ~ | + | : ~62.5 mm² |
− | :[[File:cha core group | + | :[[File:cha core group.png|500px]] |
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==== CNS Core ==== | ==== CNS Core ==== | ||
− | : ~4. | + | : ~4.4 mm² |
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− | :[[File:cha cns core die.png| | + | :[[File:cha cns core die.png|300px]] |
=== NCORE === | === NCORE === | ||
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<div style="float: left;">[[File:cha soc ncore.png|300px]]</div> | <div style="float: left;">[[File:cha soc ncore.png|300px]]</div> | ||
<div style="float: left;">[[File:cha soc ncore (2).png|300px]]</div> | <div style="float: left;">[[File:cha soc ncore (2).png|300px]]</div> | ||
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</div> | </div> | ||
Facts about "CHA - Microarchitectures - Centaur Technology"
codename | CHA + |
core count | 8 + |
designer | Centaur Technology + |
full page name | centaur/microarchitectures/cha + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | CHA + |
pipeline stages (max) | 22 + |
pipeline stages (min) | 20 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |